From e5e9e9179f353b5bcfdbba49fe9f132a617b1e8e Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Tue, 20 Nov 2012 13:27:42 -0200 Subject: [PATCH] --- yaml --- r: 345497 b: refs/heads/master c: 54075a7d75732147c32f7a99af5218f7d0f62596 h: refs/heads/master i: 345495: 88e7923d038cea7eaf00a60d58dd1899899273d8 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index 00c47b24939d..130a6090b5ed 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 13888d78c664a1f61d7b09d282f5916993827a40 +refs/heads/master: 54075a7d75732147c32f7a99af5218f7d0f62596 diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index c2ef6cdf66c3..1e405a3b6604 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -3467,7 +3467,8 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) * as some pre-programmed values are broken, * e.g. x201. */ - I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); + I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | + PF_PIPE_SEL_IVB(pipe)); I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos); I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size); }