From e74a9bfe33bf8195446d47f3dfd0f6e13dddc53f Mon Sep 17 00:00:00 2001 From: Thierry Reding Date: Mon, 1 Oct 2012 08:41:23 +0200 Subject: [PATCH] --- yaml --- r: 333109 b: refs/heads/master c: 85f8879ca4f3d26a7f473522101fb74a79bda3f2 h: refs/heads/master i: 333107: 9530194d85ca326ef41f12e4abfe710c3153c6e3 v: v3 --- [refs] | 2 +- trunk/Documentation/devicetree/bindings/pwm/imx-pwm.txt | 2 +- trunk/Documentation/devicetree/bindings/pwm/mxs-pwm.txt | 2 +- .../devicetree/bindings/pwm/nvidia,tegra20-pwm.txt | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 47dfde7150f4..7e8bf2957fbd 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: c2d476a98f71c55e9acdca1d5a1080a22c0622af +refs/heads/master: 85f8879ca4f3d26a7f473522101fb74a79bda3f2 diff --git a/trunk/Documentation/devicetree/bindings/pwm/imx-pwm.txt b/trunk/Documentation/devicetree/bindings/pwm/imx-pwm.txt index 9b9b18514b61..8522bfbccfd7 100644 --- a/trunk/Documentation/devicetree/bindings/pwm/imx-pwm.txt +++ b/trunk/Documentation/devicetree/bindings/pwm/imx-pwm.txt @@ -4,7 +4,7 @@ Required properties: - compatible: should be "fsl,-pwm" - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. The first cell specifies the per-chip index - of the PWM to use and the second cell is the duty cycle in nanoseconds. + of the PWM to use and the second cell is the period in nanoseconds. - interrupts: The interrupt for the pwm controller Example: diff --git a/trunk/Documentation/devicetree/bindings/pwm/mxs-pwm.txt b/trunk/Documentation/devicetree/bindings/pwm/mxs-pwm.txt index b16f4a57d111..d7946be6cd27 100644 --- a/trunk/Documentation/devicetree/bindings/pwm/mxs-pwm.txt +++ b/trunk/Documentation/devicetree/bindings/pwm/mxs-pwm.txt @@ -4,7 +4,7 @@ Required properties: - compatible: should be "fsl,imx23-pwm" - reg: physical base address and length of the controller's registers - #pwm-cells: should be 2. The first cell specifies the per-chip index - of the PWM to use and the second cell is the duty cycle in nanoseconds. + of the PWM to use and the second cell is the period in nanoseconds. - fsl,pwm-number: the number of PWM devices Example: diff --git a/trunk/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt b/trunk/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt index bbbeedb4ec05..01438ecd6628 100644 --- a/trunk/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt +++ b/trunk/Documentation/devicetree/bindings/pwm/nvidia,tegra20-pwm.txt @@ -7,7 +7,7 @@ Required properties: - reg: physical base address and length of the controller's registers - #pwm-cells: On Tegra the number of cells used to specify a PWM is 2. The first cell specifies the per-chip index of the PWM to use and the second - cell is the duty cycle in nanoseconds. + cell is the period in nanoseconds. Example: