From e7508505c54dc0283a898b840b3ea9c49b2aea4d Mon Sep 17 00:00:00 2001
From: Laxman Dewangan <ldewangan@nvidia.com>
Date: Sun, 6 Jan 2013 21:52:03 +0530
Subject: [PATCH] --- yaml --- r: 358502 b: refs/heads/master c:
 5ea7caf30debefc1c4319f77146288fd5e92a803 h: refs/heads/master v: v3

---
 [refs]                              |  2 +-
 trunk/drivers/dma/tegra20-apb-dma.c | 13 ++++++++++++-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 4925bc217058..8998dc46c756 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 1b140908c4cda43c653bb080c244d112e619008f
+refs/heads/master: 5ea7caf30debefc1c4319f77146288fd5e92a803
diff --git a/trunk/drivers/dma/tegra20-apb-dma.c b/trunk/drivers/dma/tegra20-apb-dma.c
index 2c46ac46e7ad..6c144814a896 100644
--- a/trunk/drivers/dma/tegra20-apb-dma.c
+++ b/trunk/drivers/dma/tegra20-apb-dma.c
@@ -1217,8 +1217,19 @@ static const struct tegra_dma_chip_data tegra30_dma_chip_data = {
 	.support_channel_pause	= false,
 };
 
-static const struct of_device_id tegra_dma_of_match[] __devinitconst = {
+/* Tegra114 specific DMA controller information */
+static const struct tegra_dma_chip_data tegra114_dma_chip_data = {
+	.nr_channels		= 32,
+	.max_dma_count		= 1024UL * 64,
+	.support_channel_pause	= true,
+};
+
+
+static const struct of_device_id tegra_dma_of_match[] = {
 	{
+		.compatible = "nvidia,tegra114-apbdma",
+		.data = &tegra114_dma_chip_data,
+	}, {
 		.compatible = "nvidia,tegra30-apbdma",
 		.data = &tegra30_dma_chip_data,
 	}, {