diff --git a/[refs] b/[refs]
index 543820a1e6e5..e5c15a3910d7 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: eaf4f33feca2704ad1d06f1ef6b427712c506cc0
+refs/heads/master: 6aaa8b5570c7b5b9eb8913ec80263a1012b1dd66
diff --git a/trunk/arch/arm/kernel/kprobes.h b/trunk/arch/arm/kernel/kprobes.h
index a84b14d8cdc8..5e2485c4cacd 100644
--- a/trunk/arch/arm/kernel/kprobes.h
+++ b/trunk/arch/arm/kernel/kprobes.h
@@ -68,6 +68,31 @@ void __init find_str_pc_offset(void);
 #endif
 
 
+/*
+ * Update ITSTATE after normal execution of an IT block instruction.
+ *
+ * The 8 IT state bits are split into two parts in CPSR:
+ *	ITSTATE<1:0> are in CPSR<26:25>
+ *	ITSTATE<7:2> are in CPSR<15:10>
+ */
+static inline unsigned long it_advance(unsigned long cpsr)
+	{
+	if ((cpsr & 0x06000400) == 0) {
+		/* ITSTATE<2:0> == 0 means end of IT block, so clear IT state */
+		cpsr &= ~PSR_IT_MASK;
+	} else {
+		/* We need to shift left ITSTATE<4:0> */
+		const unsigned long mask = 0x06001c00;  /* Mask ITSTATE<4:0> */
+		unsigned long it = cpsr & mask;
+		it <<= 1;
+		it |= it >> (27 - 10);  /* Carry ITSTATE<2> to correct place */
+		it &= mask;
+		cpsr &= ~mask;
+		cpsr |= it;
+	}
+	return cpsr;
+}
+
 /*
  * Test if load/store instructions writeback the address register.
  * if P (bit 24) == 0 or W (bit 21) == 1