From e8f16999474c80cf16a052ddb4cdcf653a4d5828 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= Date: Sun, 17 Mar 2013 19:08:15 +0100 Subject: [PATCH] --- yaml --- r: 369655 b: refs/heads/master c: fc6ab1e0c032f3ae3f20e405c5ca51f20540b52c h: refs/heads/master i: 369653: 4addd2d277d264e255990bcc8723e32a67cb4a0b 369651: 84e7dd0052c6222a22a3d27d02c0b14d93cd0abf 369647: ada978b1ca20f1661391335dced62d2663f6d788 v: v3 --- [refs] | 2 +- trunk/drivers/net/wireless/b43/phy_ht.h | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 868880f60845..46419ec9274c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: dc3c4e127168dff9dbef0b22351b592a81fe5bfb +refs/heads/master: fc6ab1e0c032f3ae3f20e405c5ca51f20540b52c diff --git a/trunk/drivers/net/wireless/b43/phy_ht.h b/trunk/drivers/net/wireless/b43/phy_ht.h index 9b2408efb224..6cae370d1018 100644 --- a/trunk/drivers/net/wireless/b43/phy_ht.h +++ b/trunk/drivers/net/wireless/b43/phy_ht.h @@ -23,6 +23,9 @@ #define B43_PHY_HT_SAMP_WAIT_CNT 0x0C5 /* Sample wait count */ #define B43_PHY_HT_SAMP_DEP_CNT 0x0C6 /* Sample depth count */ #define B43_PHY_HT_SAMP_STAT 0x0C7 /* Sample status */ +#define B43_PHY_HT_EST_PWR_C1 0x118 +#define B43_PHY_HT_EST_PWR_C2 0x119 +#define B43_PHY_HT_EST_PWR_C3 0x11A #define B43_PHY_HT_TSSIMODE 0x122 /* TSSI mode */ #define B43_PHY_HT_TSSIMODE_EN 0x0001 /* TSSI enable */ #define B43_PHY_HT_TSSIMODE_PDEN 0x0002 /* Power det enable */ @@ -53,6 +56,8 @@ #define B43_PHY_HT_TXPCTL_TARG_PWR_C1_SHIFT 0 #define B43_PHY_HT_TXPCTL_TARG_PWR_C2 0xFF00 /* Power 1 */ #define B43_PHY_HT_TXPCTL_TARG_PWR_C2_SHIFT 8 +#define B43_PHY_HT_TX_PCTL_STATUS_C1 0x1ED +#define B43_PHY_HT_TX_PCTL_STATUS_C2 0x1EE #define B43_PHY_HT_TXPCTL_CMD_C2 0x222 #define B43_PHY_HT_TXPCTL_CMD_C2_INIT 0x007F #define B43_PHY_HT_RSSI_C1 0x219 @@ -97,6 +102,7 @@ #define B43_PHY_HT_TXPCTL_TARG_PWR2 B43_PHY_EXTG(0x166) /* TX power control target power */ #define B43_PHY_HT_TXPCTL_TARG_PWR2_C3 0x00FF #define B43_PHY_HT_TXPCTL_TARG_PWR2_C3_SHIFT 0 +#define B43_PHY_HT_TX_PCTL_STATUS_C3 B43_PHY_EXTG(0x169) #define B43_PHY_HT_TEST B43_PHY_N_BMODE(0x00A)