From e9add4a648a9230921ba32a0f0e6a6b8924b2d15 Mon Sep 17 00:00:00 2001 From: Will Deacon Date: Fri, 18 Feb 2011 16:36:35 +0100 Subject: [PATCH] --- yaml --- r: 233482 b: refs/heads/master c: 9a27c27ce49df72b1b0062e2ad192a804e1b069b h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/Kconfig | 10 ++++++++++ trunk/arch/arm/mm/proc-v7.S | 6 ++++++ 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index f9be34f4d6d6..273fead69caa 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 71efb063f4a145ae420be054f5a91dcf7c19b375 +refs/heads/master: 9a27c27ce49df72b1b0062e2ad192a804e1b069b diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig index ba9fc213f344..166efa2a19cd 100644 --- a/trunk/arch/arm/Kconfig +++ b/trunk/arch/arm/Kconfig @@ -1177,6 +1177,16 @@ config ARM_ERRATA_743622 visible impact on the overall performance or power consumption of the processor. +config ARM_ERRATA_751472 + bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" + depends on CPU_V7 && SMP + help + This option enables the workaround for the 751472 Cortex-A9 (prior + to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the + completion of a following broadcasted operation if the second + operation is received by a CPU before the ICIALLUIS has completed, + potentially leading to corrupted entries in the cache or TLB. + config ARM_ERRATA_753970 bool "ARM errata: cache sync operation may be faulty" depends on CACHE_PL310 diff --git a/trunk/arch/arm/mm/proc-v7.S b/trunk/arch/arm/mm/proc-v7.S index 0c1172b56b4e..8e3356239136 100644 --- a/trunk/arch/arm/mm/proc-v7.S +++ b/trunk/arch/arm/mm/proc-v7.S @@ -264,6 +264,12 @@ __v7_setup: orreq r10, r10, #1 << 6 @ set bit #6 mcreq p15, 0, r10, c15, c0, 1 @ write diagnostic register #endif +#ifdef CONFIG_ARM_ERRATA_751472 + cmp r6, #0x30 @ present prior to r3p0 + mrclt p15, 0, r10, c15, c0, 1 @ read diagnostic register + orrlt r10, r10, #1 << 11 @ set bit #11 + mcrlt p15, 0, r10, c15, c0, 1 @ write diagnostic register +#endif 3: mov r10, #0 #ifdef HARVARD_CACHE