From e9b411d3aeb34d44225eeb05b1b5845e27e4c167 Mon Sep 17 00:00:00 2001 From: Mythri P K Date: Thu, 8 Sep 2011 19:06:22 +0530 Subject: [PATCH] --- yaml --- r: 271407 b: refs/heads/master c: 7c1f1ecac9240663db357ae0f30761a7ee7c8463 h: refs/heads/master i: 271405: d4408bcf24efdd3dc5884d6426391d775f6449ce 271403: c3d2494d837914d171f4c2b5c6aa306627364b31 271399: 91c497a20c056a357785e819698f2ed82c7c5f4e 271391: ef59c5f46d9577f3bfd993a92a3f7de99b5cb0a1 v: v3 --- [refs] | 2 +- trunk/drivers/video/omap2/dss/hdmi.c | 10 ++++++++++ trunk/drivers/video/omap2/dss/hdmi.h | 10 ---------- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/[refs] b/[refs] index cdddccf000c8..e9904c01376c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 94c52987d293ec2aeb75993a3e33b7c36159668c +refs/heads/master: 7c1f1ecac9240663db357ae0f30761a7ee7c8463 diff --git a/trunk/drivers/video/omap2/dss/hdmi.c b/trunk/drivers/video/omap2/dss/hdmi.c index bf76c87024b2..96a0ac941126 100644 --- a/trunk/drivers/video/omap2/dss/hdmi.c +++ b/trunk/drivers/video/omap2/dss/hdmi.c @@ -50,6 +50,16 @@ #define HDMI_PLLCTRL 0x200 #define HDMI_PHY 0x300 +/* HDMI EDID Length move this */ +#define HDMI_EDID_MAX_LENGTH 256 +#define EDID_TIMING_DESCRIPTOR_SIZE 0x12 +#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 +#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 +#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 +#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 + +#define OMAP_HDMI_TIMINGS_NB 34 + static struct { struct mutex lock; struct omap_display_platform_data *pdata; diff --git a/trunk/drivers/video/omap2/dss/hdmi.h b/trunk/drivers/video/omap2/dss/hdmi.h index cb50f6a3ad09..2d4a22eca9c6 100644 --- a/trunk/drivers/video/omap2/dss/hdmi.h +++ b/trunk/drivers/video/omap2/dss/hdmi.h @@ -182,16 +182,6 @@ struct hdmi_reg { u16 idx; }; #define HDMI_TXPHY_POWER_CTRL HDMI_REG(0x8) #define HDMI_TXPHY_PAD_CFG_CTRL HDMI_REG(0xC) -/* HDMI EDID Length */ -#define HDMI_EDID_MAX_LENGTH 256 -#define EDID_TIMING_DESCRIPTOR_SIZE 0x12 -#define EDID_DESCRIPTOR_BLOCK0_ADDRESS 0x36 -#define EDID_DESCRIPTOR_BLOCK1_ADDRESS 0x80 -#define EDID_SIZE_BLOCK0_TIMING_DESCRIPTOR 4 -#define EDID_SIZE_BLOCK1_TIMING_DESCRIPTOR 4 - -#define OMAP_HDMI_TIMINGS_NB 34 - #define REG_FLD_MOD(base, idx, val, start, end) \ hdmi_write_reg(base, idx, FLD_MOD(hdmi_read_reg(base, idx),\ val, start, end))