From ea51bf53a743f5212fc22f7900e99d3f52d16063 Mon Sep 17 00:00:00 2001
From: Ben Widawsky <ben@bwidawsk.net>
Date: Fri, 7 Sep 2012 19:43:41 -0700
Subject: [PATCH] --- yaml --- r: 329475 b: refs/heads/master c:
 d5570a72439b2d972c915208266440c2f330d03d h: refs/heads/master i:   329473:
 3b1bc9830261ffeea78cedb77c358cdf9349885d   329471:
 c541d921b8ac97c466c04a237b1cc29925cbf072 v: v3

---
 [refs]                                | 2 +-
 trunk/drivers/gpu/drm/i915/intel_pm.c | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index ba827ac8aea3..0c76a7e213c3 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: df6eedc81d43c2245885c6baeb28d488c8a4dea4
+refs/heads/master: d5570a72439b2d972c915208266440c2f330d03d
diff --git a/trunk/drivers/gpu/drm/i915/intel_pm.c b/trunk/drivers/gpu/drm/i915/intel_pm.c
index 36c64091bc90..4e86037ae6b4 100644
--- a/trunk/drivers/gpu/drm/i915/intel_pm.c
+++ b/trunk/drivers/gpu/drm/i915/intel_pm.c
@@ -2338,6 +2338,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
 	 */
 	I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
 
+	POSTING_READ(GEN6_RPNSWREQ);
+
 	dev_priv->rps.cur_delay = val;
 
 	trace_intel_gpu_freq_change(val * 50);