From eaafa605b160f2c08fd395f263a331d4f2eac1c4 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Thu, 29 Nov 2012 15:59:35 +0100 Subject: [PATCH] --- yaml --- r: 357906 b: refs/heads/master c: 2f0c2ad18b88691496e23d1ddbc2d0af8f6df5fa h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/intel_display.c | 9 +-------- 2 files changed, 2 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index 91f16a8e9300..8c0a6f85d140 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ff50afe9aceb6264a4fbe40459da75170fb9a2a2 +refs/heads/master: 2f0c2ad18b88691496e23d1ddbc2d0af8f6df5fa diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index f3e58a43886b..953796c84fbd 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -5345,15 +5345,8 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, } else intel_put_pch_pll(intel_crtc); - if (is_dp && !is_cpu_edp) { + if (is_dp && !is_cpu_edp) intel_dp_set_m_n(crtc, mode, adjusted_mode); - } else { - /* For non-DP output, clear any trans DP clock recovery setting.*/ - I915_WRITE(TRANSDATA_M1(pipe), 0); - I915_WRITE(TRANSDATA_N1(pipe), 0); - I915_WRITE(TRANSDPLINK_M1(pipe), 0); - I915_WRITE(TRANSDPLINK_N1(pipe), 0); - } for_each_encoder_on_crtc(dev, crtc, encoder) if (encoder->pre_pll_enable)