From eab5f3cf48454c2f96c741ad289ab47f808a0509 Mon Sep 17 00:00:00 2001
From: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Date: Sun, 30 Oct 2005 14:59:35 -0800
Subject: [PATCH] --- yaml --- r: 11760 b: refs/heads/master c:
 434440a2804639f11858d9d384c9505927feb186 h: refs/heads/master v: v3

---
 [refs]                                 |  2 +-
 trunk/arch/i386/kernel/cpu/mcheck/p6.c | 11 ++++++++---
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/[refs] b/[refs]
index 935764b159f7..d53b9f99109a 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 251e6912df43df54570ed68aade703b329c6cd5b
+refs/heads/master: 434440a2804639f11858d9d384c9505927feb186
diff --git a/trunk/arch/i386/kernel/cpu/mcheck/p6.c b/trunk/arch/i386/kernel/cpu/mcheck/p6.c
index 3c035b8fa3d9..979b18bc95c1 100644
--- a/trunk/arch/i386/kernel/cpu/mcheck/p6.c
+++ b/trunk/arch/i386/kernel/cpu/mcheck/p6.c
@@ -102,11 +102,16 @@ void __devinit intel_p6_mcheck_init(struct cpuinfo_x86 *c)
 		wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 	nr_mce_banks = l & 0xff;
 
-	/* Don't enable bank 0 on intel P6 cores, it goes bang quickly. */
-	for (i=1; i<nr_mce_banks; i++) {
+	/*
+	 * Following the example in IA-32 SDM Vol 3:
+	 * - MC0_CTL should not be written
+	 * - Status registers on all banks should be cleared on reset
+	 */
+	for (i=1; i<nr_mce_banks; i++)
 		wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
+
+	for (i=0; i<nr_mce_banks; i++)
 		wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
-	}
 
 	set_in_cr4 (X86_CR4_MCE);
 	printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",