From ebb50ee6adbc9bc338a652ec47989e6cb39124be Mon Sep 17 00:00:00 2001 From: Michael Witten Date: Mon, 29 Aug 2011 16:00:55 +0000 Subject: [PATCH] --- yaml --- r: 275222 b: refs/heads/master c: 2d43f5d667273ba4975cb79782a46aa374dd8607 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/Documentation/DocBook/drm.tmpl | 5 +++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 7f867b2c59d2..4980a0b6eeaf 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 0c2d91a80a156208d2f9f3dfb01871ebcf4a9338 +refs/heads/master: 2d43f5d667273ba4975cb79782a46aa374dd8607 diff --git a/trunk/Documentation/DocBook/drm.tmpl b/trunk/Documentation/DocBook/drm.tmpl index c358367f9f85..ba20f9fbb62b 100644 --- a/trunk/Documentation/DocBook/drm.tmpl +++ b/trunk/Documentation/DocBook/drm.tmpl @@ -720,8 +720,9 @@ void intel_crt_init(struct drm_device *dev) provides memory to back each object. When mapped into the GTT or used in a command buffer, the backing pages for an object are flushed to memory and marked write combined so as to be coherent - with the GPU. Likewise, when the GPU finishes rendering to an object, - if the CPU accesses it, it must be made coherent with the CPU's view + with the GPU. Likewise, if the CPU accesses an object after the GPU + has finished rendering to the object, then the object must be made + coherent with the CPU's view of memory, usually involving GPU cache flushing of various kinds. This core CPU<->GPU coherency management is provided by the GEM set domain function, which evaluates an object's current domain and