From ec32217c6b06e1176d38405e6b36e95b48a047c5 Mon Sep 17 00:00:00 2001
From: Matt Carlson <mcarlson@broadcom.com>
Date: Mon, 2 Aug 2010 11:25:55 +0000
Subject: [PATCH] --- yaml --- r: 203990 b: refs/heads/master c:
 6de34cb963a934953fdd365937b4b75959256602 h: refs/heads/master v: v3

---
 [refs]                  | 2 +-
 trunk/drivers/net/tg3.c | 3 +--
 2 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index ea58eec3b151..9cb14178afcd 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 83bf2e4089bebc2c7fd14a79de5954b26fe8d4af
+refs/heads/master: 6de34cb963a934953fdd365937b4b75959256602
diff --git a/trunk/drivers/net/tg3.c b/trunk/drivers/net/tg3.c
index b26a57782939..98ca0d20d206 100644
--- a/trunk/drivers/net/tg3.c
+++ b/trunk/drivers/net/tg3.c
@@ -7002,8 +7002,7 @@ static int tg3_chip_reset(struct tg3 *tp)
 		 * Older PCIe devices only support the 128 byte
 		 * MPS setting.  Enforce the restriction.
 		 */
-		if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
-		    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
+		if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT))
 			val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
 		pci_write_config_word(tp->pdev,
 				      tp->pcie_cap + PCI_EXP_DEVCTL,