From edd5bfc2f2e5ddf6404bf7a500e260e35e984b5d Mon Sep 17 00:00:00 2001 From: "H. Peter Anvin" Date: Thu, 14 Feb 2008 14:56:45 -0800 Subject: [PATCH] --- yaml --- r: 86337 b: refs/heads/master c: 959b3be64cab9160cd74532a49b89cdd918d38e9 h: refs/heads/master i: 86335: 0008f7d85dd3a930f9522d9b9d6c964a2ac41f9c v: v3 --- [refs] | 2 +- trunk/arch/x86/Kconfig.cpu | 11 ++++++++++- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index c149adfba25a..a8a72c1fff98 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 7343b3b3a627eb30e24e921f004f659c8ebb91c5 +refs/heads/master: 959b3be64cab9160cd74532a49b89cdd918d38e9 diff --git a/trunk/arch/x86/Kconfig.cpu b/trunk/arch/x86/Kconfig.cpu index 86fd2a0e4597..6d50064db182 100644 --- a/trunk/arch/x86/Kconfig.cpu +++ b/trunk/arch/x86/Kconfig.cpu @@ -377,9 +377,18 @@ config X86_OOSTORE def_bool y depends on (MWINCHIP3D || MWINCHIP2 || MWINCHIPC6) && MTRR +# +# P6_NOPs are a relatively minor optimization that require a family >= +# 6 processor, except that it is broken on certain VIA chips. +# Furthermore, AMD chips prefer a totally different sequence of NOPs +# (which work on all CPUs). As a result, disallow these if we're +# compiling X86_GENERIC but not X86_64 (these NOPs do work on all +# x86-64 capable chips); the list of processors in the right-hand clause +# are the cores that benefit from this optimization. +# config X86_P6_NOP def_bool y - depends on (M686 || MPENTIUMII || MPENTIUMIII || MPENTIUMM || MCORE2 || PENTIUM4) + depends on (X86_64 || !X86_GENERIC) && (M686 || MPENTIUMII || MPENTIUMIII || MPENTIUMM || MCORE2 || PENTIUM4) config X86_TSC def_bool y