From edde4af24825e29b29ba848a9b84e7ae9c7877fd Mon Sep 17 00:00:00 2001
From: Johannes Berg <johannes@sipsolutions.net>
Date: Wed, 7 Nov 2007 23:59:44 +1100
Subject: [PATCH] --- yaml --- r: 73329 b: refs/heads/master c:
 2e6f40deb7dfdc40358fc9ecf07bf71ed553e5ac h: refs/heads/master i:   73327:
 6606f5d4a2448952b4a426fac594e1f7b1db2d67 v: v3

---
 [refs]                                | 2 +-
 trunk/arch/powerpc/kernel/swsusp_32.S | 2 ++
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/[refs] b/[refs]
index 2e666e8a7784..5d91c35e69d4 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 67b60518b0ff5cd666c7650eb09f0ef41f838106
+refs/heads/master: 2e6f40deb7dfdc40358fc9ecf07bf71ed553e5ac
diff --git a/trunk/arch/powerpc/kernel/swsusp_32.S b/trunk/arch/powerpc/kernel/swsusp_32.S
index 69e8f86aa4f8..77fc76607ab2 100644
--- a/trunk/arch/powerpc/kernel/swsusp_32.S
+++ b/trunk/arch/powerpc/kernel/swsusp_32.S
@@ -133,10 +133,12 @@ _GLOBAL(swsusp_arch_suspend)
 /* Resume code */
 _GLOBAL(swsusp_arch_resume)
 
+#ifdef CONFIG_ALTIVEC
 	/* Stop pending alitvec streams and memory accesses */
 BEGIN_FTR_SECTION
 	DSSALL
 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
+#endif
  	sync
 
 	/* Disable MSR:DR to make sure we don't take a TLB or