From efa5286838c29eba1c7ff6a22bcd28f187fbe4ed Mon Sep 17 00:00:00 2001 From: Heiko Stuebner Date: Wed, 7 Mar 2012 02:00:04 -0800 Subject: [PATCH] --- yaml --- r: 295701 b: refs/heads/master c: 9edc12a1a9db50fd7659463adf5a0e1eb5f2ce0d h: refs/heads/master i: 295699: 8fe9e39fd1421e5e1c2d4ee8e35bf7d340def879 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-s3c24xx/common-s3c2443.c | 28 +++++++++++++++++--- 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index d47f19f56398..1f429028e489 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b681bfcf484519112ed67ceaed94fdaca929aaef +refs/heads/master: 9edc12a1a9db50fd7659463adf5a0e1eb5f2ce0d diff --git a/trunk/arch/arm/mach-s3c24xx/common-s3c2443.c b/trunk/arch/arm/mach-s3c24xx/common-s3c2443.c index 5e863bff5c7f..46795db2af41 100644 --- a/trunk/arch/arm/mach-s3c24xx/common-s3c2443.c +++ b/trunk/arch/arm/mach-s3c24xx/common-s3c2443.c @@ -187,6 +187,25 @@ static struct clk_ops clk_h_ops = { .get_rate = s3c2443_hclkdiv_getrate, }; +/* pclk divider + * + * divides the hclk and provides the pclk. + */ + +static unsigned long s3c2443_pclkdiv_getrate(struct clk *clk) +{ + unsigned long rate = clk_get_rate(clk->parent); + unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); + + clkdiv0 = ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 1 : 0); + + return rate / (clkdiv0 + 1); +} + +static struct clk_ops clk_p_ops = { + .get_rate = s3c2443_pclkdiv_getrate, +}; + /* armdiv * * this clock is sourced from msysclk and can have a number of @@ -549,7 +568,6 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) { unsigned long epllcon = __raw_readl(S3C2443_EPLLCON); unsigned long mpllcon = __raw_readl(S3C2443_MPLLCON); - unsigned long clkdiv0 = __raw_readl(S3C2443_CLKDIV0); struct clk *xtal_clk; unsigned long xtal; unsigned long pll; @@ -567,7 +585,7 @@ void __init_or_cpufreq s3c2443_common_setup_clocks(pll_fn get_mpll) fclk = clk_get_rate(&clk_armdiv); hclk = clk_get_rate(&clk_h); - pclk = hclk / ((clkdiv0 & S3C2443_CLKDIV0_HALF_PCLK) ? 2 : 1); + pclk = clk_get_rate(&clk_p); s3c24xx_setup_clocks(fclk, hclk, pclk); @@ -630,11 +648,13 @@ void __init s3c2443_common_init_clocks(int xtal, pll_fn get_mpll, nr_armdiv = nr_divs; armdivmask = divmask; - /* s3c2443 parents h and p clocks from prediv */ + /* s3c2443 parents h clock from prediv */ clk_h.parent = &clk_prediv; clk_h.ops = &clk_h_ops; - clk_p.parent = &clk_prediv; + /* and p clock from h clock */ + clk_p.parent = &clk_h; + clk_p.ops = &clk_p_ops; clk_usb_bus.parent = &clk_usb_bus_host.clk; clk_epll.parent = &clk_epllref.clk;