From f13694210e5d71b8277ca4c288f8b6eb94c9d202 Mon Sep 17 00:00:00 2001 From: Eugeni Dodonov Date: Fri, 13 Apr 2012 17:08:38 -0300 Subject: [PATCH] --- yaml --- r: 307169 b: refs/heads/master c: ef4d084fae9d4719bc52f97e15e41e1602e3bc6e h: refs/heads/master i: 307167: c32f6e86f28cb0f066316bf135104109d1bb4d95 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 4 ++++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 1fda18560b5a..13fa2d959830 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: dc04a61a0503613e17bc1405538fec52e74d4b43 +refs/heads/master: ef4d084fae9d4719bc52f97e15e41e1602e3bc6e diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index bc1a5c60822e..0668815d05d7 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -4191,6 +4191,10 @@ #define WRPLL_PLL_SELECT_SSC (0x01<<28) #define WRPLL_PLL_SELECT_NON_SCC (0x02<<28) #define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28) +/* WRPLL divider programming */ +#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0) +#define WRPLL_DIVIDER_POST(x) ((x)<<8) +#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16) /* Port clock selection */ #define PORT_CLK_SEL_A 0x46100