From f1502d917715ab90b9cdb8df5d85722c66b6749c Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Fri, 13 Nov 2009 14:12:16 -0600 Subject: [PATCH] --- yaml --- r: 176948 b: refs/heads/master c: b3a70f0bc32d1b70584bcaa6019fa4260b0da92e h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/mtd/nand/fsl_elbc_nand.c | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 2f245fc3683e..70563f51c961 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 54c69cc25064c1d333a12b5883aaa3bfa3041dee +refs/heads/master: b3a70f0bc32d1b70584bcaa6019fa4260b0da92e diff --git a/trunk/drivers/mtd/nand/fsl_elbc_nand.c b/trunk/drivers/mtd/nand/fsl_elbc_nand.c index ddd37d2554ed..58db27855126 100644 --- a/trunk/drivers/mtd/nand/fsl_elbc_nand.c +++ b/trunk/drivers/mtd/nand/fsl_elbc_nand.c @@ -946,6 +946,13 @@ static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl) { struct fsl_lbc_regs __iomem *lbc = ctrl->regs; + /* + * NAND transactions can tie up the bus for a long time, so set the + * bus timeout to max by clearing LBCR[BMT] (highest base counter + * value) and setting LBCR[BMTPS] to the highest prescaler value. + */ + clrsetbits_be32(&lbc->lbcr, LBCR_BMT, 15); + /* clear event registers */ setbits32(&lbc->ltesr, LTESR_NAND_MASK); out_be32(&lbc->lteatr, 0);