diff --git a/[refs] b/[refs]
index 3ef5573ff472..8a5427990cc0 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 0456ec4ff2b832ab9ff476ed687fea704500f1cd
+refs/heads/master: c0fe7b099931c6c05c98a05c277185ee25254f35
diff --git a/trunk/arch/powerpc/kvm/bookehv_interrupts.S b/trunk/arch/powerpc/kvm/bookehv_interrupts.S
index 57e2fa414444..909e96e0650c 100644
--- a/trunk/arch/powerpc/kvm/bookehv_interrupts.S
+++ b/trunk/arch/powerpc/kvm/bookehv_interrupts.S
@@ -580,7 +580,6 @@ lightweight_exit:
 	mtlr	r3
 	mtxer	r5
 	mtctr	r6
-	mtcr	r7
 	mtsrr0	r8
 	mtsrr1	r9
 
@@ -588,14 +587,20 @@ lightweight_exit:
 	/* save enter time */
 1:
 	mfspr	r6, SPRN_TBRU
-	mfspr	r7, SPRN_TBRL
+	mfspr	r9, SPRN_TBRL
 	mfspr	r8, SPRN_TBRU
 	cmpw	r8, r6
-	PPC_STL	r7, VCPU_TIMING_LAST_ENTER_TBL(r4)
+	PPC_STL	r9, VCPU_TIMING_LAST_ENTER_TBL(r4)
 	bne	1b
 	PPC_STL	r8, VCPU_TIMING_LAST_ENTER_TBU(r4)
 #endif
 
+	/*
+	 * Don't execute any instruction which can change CR after
+	 * below instruction.
+	 */
+	mtcr	r7
+
 	/* Finish loading guest volatiles and jump to guest. */
 	PPC_LL	r5, VCPU_GPR(r5)(r4)
 	PPC_LL	r6, VCPU_GPR(r6)(r4)