From f3441ee0dcec44bdf1dd0ffe1c55b8c00c685978 Mon Sep 17 00:00:00 2001 From: Matt Evans Date: Mon, 5 Jul 2010 17:36:32 +0000 Subject: [PATCH] --- yaml --- r: 200902 b: refs/heads/master c: 219a92a4c40db2fac604f63bce9a5a3fe1967879 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-s5p6442/clock.c | 2 +- trunk/arch/arm/mach-s5pv210/clock.c | 115 ++++++++---------- trunk/arch/arm/plat-s5p/irq-eint.c | 2 +- .../arm/plat-samsung/include/plat/sdhci.h | 4 +- trunk/arch/powerpc/kernel/perf_event.c | 5 +- 6 files changed, 61 insertions(+), 69 deletions(-) diff --git a/[refs] b/[refs] index f806e9d147b0..3c06e24dc741 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 67415020950046e32f520c1447e79ebebbf447ac +refs/heads/master: 219a92a4c40db2fac604f63bce9a5a3fe1967879 diff --git a/trunk/arch/arm/mach-s5p6442/clock.c b/trunk/arch/arm/mach-s5p6442/clock.c index 087e57f20ad5..3aadbf42c112 100644 --- a/trunk/arch/arm/mach-s5p6442/clock.c +++ b/trunk/arch/arm/mach-s5p6442/clock.c @@ -294,7 +294,7 @@ void __init_or_cpufreq s5p6442_setup_clocks(void) mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P_MPLL_CON), pll_4502); epll = s5p_get_pll45xx(xtal, __raw_readl(S5P_EPLL_CON), pll_4500); - printk(KERN_INFO "S5P6442: PLL settings, A=%ld, M=%ld, E=%ld", + printk(KERN_INFO "S5P6440: PLL settings, A=%ld, M=%ld, E=%ld", apll, mpll, epll); clk_fout_apll.rate = apll; diff --git a/trunk/arch/arm/mach-s5pv210/clock.c b/trunk/arch/arm/mach-s5pv210/clock.c index af91fefef2c6..154bca4abc09 100644 --- a/trunk/arch/arm/mach-s5pv210/clock.c +++ b/trunk/arch/arm/mach-s5pv210/clock.c @@ -183,11 +183,6 @@ static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable) return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); } -static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable) -{ - return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable); -} - static struct clk clk_sclk_hdmi27m = { .name = "sclk_hdmi27m", .id = -1, @@ -411,14 +406,14 @@ static struct clk init_clocks_disable[] = { .id = 0, .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 5), + .ctrlbit = (1<<4), }, { .name = "i2s_v32", .id = 1, .parent = &clk_p, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 6), - }, + .ctrlbit = (1<<4), + } }; static struct clk init_clocks[] = { @@ -434,25 +429,25 @@ static struct clk init_clocks[] = { .id = 0, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 17), + .ctrlbit = (1<<7), }, { .name = "uart", .id = 1, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 18), + .ctrlbit = (1<<8), }, { .name = "uart", .id = 2, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 19), + .ctrlbit = (1<<9), }, { .name = "uart", .id = 3, .parent = &clk_pclk_psys.clk, .enable = s5pv210_clk_ip3_ctrl, - .ctrlbit = (1 << 20), + .ctrlbit = (1<<10), }, }; @@ -502,8 +497,8 @@ static struct clksrc_clk clk_sclk_dac = { .clk = { .name = "sclk_dac", .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 2), + .ctrlbit = (1 << 10), + .enable = s5pv210_clk_ip1_ctrl, }, .sources = &clkset_sclk_dac, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 }, @@ -532,8 +527,8 @@ static struct clksrc_clk clk_sclk_hdmi = { .clk = { .name = "sclk_hdmi", .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 0), + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 11), }, .sources = &clkset_sclk_hdmi, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, @@ -570,8 +565,8 @@ static struct clksrc_clk clk_sclk_audio0 = { .clk = { .name = "sclk_audio", .id = 0, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 24), + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 4), }, .sources = &clkset_sclk_audio0, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 }, @@ -599,8 +594,8 @@ static struct clksrc_clk clk_sclk_audio1 = { .clk = { .name = "sclk_audio", .id = 1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 25), + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 5), }, .sources = &clkset_sclk_audio1, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 }, @@ -628,8 +623,8 @@ static struct clksrc_clk clk_sclk_audio2 = { .clk = { .name = "sclk_audio", .id = 2, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 26), + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 6), }, .sources = &clkset_sclk_audio2, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 }, @@ -685,8 +680,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "uclk1", .id = 0, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 12), + .ctrlbit = (1<<17), + .enable = s5pv210_clk_ip3_ctrl, }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, @@ -695,8 +690,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "uclk1", .id = 1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 13), + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 18), }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, @@ -705,8 +700,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "uclk1", .id = 2, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 14), + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 19), }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, @@ -715,8 +710,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "uclk1", .id = 3, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 15), + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 20), }, .sources = &clkset_uart, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, @@ -725,8 +720,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_mixer", .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 1), + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 9), }, .sources = &clkset_sclk_mixer, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, @@ -743,8 +738,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_fimc", .id = 0, - .enable = s5pv210_clk_mask1_ctrl, - .ctrlbit = (1 << 2), + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 24), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 }, @@ -753,8 +748,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_fimc", .id = 1, - .enable = s5pv210_clk_mask1_ctrl, - .ctrlbit = (1 << 3), + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 25), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 }, @@ -763,8 +758,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_fimc", .id = 2, - .enable = s5pv210_clk_mask1_ctrl, - .ctrlbit = (1 << 4), + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 26), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 }, @@ -773,8 +768,6 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_cam", .id = 0, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 3), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 }, @@ -783,8 +776,6 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_cam", .id = 1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 4), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 }, @@ -793,8 +784,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_fimd", .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 5), + .enable = s5pv210_clk_ip1_ctrl, + .ctrlbit = (1 << 0), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, @@ -803,8 +794,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_mmc", .id = 0, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 8), + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 16), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, @@ -813,8 +804,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_mmc", .id = 1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 9), + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 17), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, @@ -823,8 +814,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_mmc", .id = 2, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 10), + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 18), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, @@ -833,8 +824,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_mmc", .id = 3, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 11), + .enable = s5pv210_clk_ip2_ctrl, + .ctrlbit = (1 << 19), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, @@ -873,8 +864,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_csis", .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 6), + .enable = s5pv210_clk_ip0_ctrl, + .ctrlbit = (1 << 31), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, @@ -883,8 +874,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_spi", .id = 0, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 16), + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 12), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, @@ -893,8 +884,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_spi", .id = 1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 17), + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 13), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, @@ -903,8 +894,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_pwi", .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 29), + .enable = &s5pv210_clk_ip4_ctrl, + .ctrlbit = (1 << 2), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 }, @@ -913,8 +904,8 @@ static struct clksrc_clk clksrcs[] = { .clk = { .name = "sclk_pwm", .id = -1, - .enable = s5pv210_clk_mask0_ctrl, - .ctrlbit = (1 << 19), + .enable = s5pv210_clk_ip3_ctrl, + .ctrlbit = (1 << 23), }, .sources = &clkset_group2, .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, diff --git a/trunk/arch/arm/plat-s5p/irq-eint.c b/trunk/arch/arm/plat-s5p/irq-eint.c index f36cd3327025..e56c8075df97 100644 --- a/trunk/arch/arm/plat-s5p/irq-eint.c +++ b/trunk/arch/arm/plat-s5p/irq-eint.c @@ -71,7 +71,7 @@ static int s5p_irq_eint_set_type(unsigned int irq, unsigned int type) break; case IRQ_TYPE_EDGE_FALLING: - newvalue = S5P_EXTINT_FALLEDGE; + newvalue = S5P_EXTINT_RISEEDGE; break; case IRQ_TYPE_EDGE_BOTH: diff --git a/trunk/arch/arm/plat-samsung/include/plat/sdhci.h b/trunk/arch/arm/plat-samsung/include/plat/sdhci.h index 016674fa20dd..13f9fb20900a 100644 --- a/trunk/arch/arm/plat-samsung/include/plat/sdhci.h +++ b/trunk/arch/arm/plat-samsung/include/plat/sdhci.h @@ -166,10 +166,8 @@ static inline void s3c6410_default_sdhci2(void) { } #else static inline void s3c6410_default_sdhci0(void) { } static inline void s3c6410_default_sdhci1(void) { } -static inline void s3c6410_default_sdhci2(void) { } static inline void s3c6400_default_sdhci0(void) { } static inline void s3c6400_default_sdhci1(void) { } -static inline void s3c6400_default_sdhci2(void) { } #endif /* CONFIG_S3C64XX_SETUP_SDHCI */ @@ -241,7 +239,7 @@ static inline void s5pv210_default_sdhci0(void) s3c_hsmmc0_def_platdata.cfg_card = s5pv210_setup_sdhci_cfg_card; } #else -static inline void s5pv210_default_sdhci0(void) { } +static inline void s5pc100_default_sdhci0(void) { } #endif /* CONFIG_S3C_DEV_HSMMC */ #ifdef CONFIG_S3C_DEV_HSMMC1 diff --git a/trunk/arch/powerpc/kernel/perf_event.c b/trunk/arch/powerpc/kernel/perf_event.c index 43b83c35cf54..5c14ffe51258 100644 --- a/trunk/arch/powerpc/kernel/perf_event.c +++ b/trunk/arch/powerpc/kernel/perf_event.c @@ -791,8 +791,11 @@ static void power_pmu_disable(struct perf_event *event) cpuhw = &__get_cpu_var(cpu_hw_events); for (i = 0; i < cpuhw->n_events; ++i) { if (event == cpuhw->event[i]) { - while (++i < cpuhw->n_events) + while (++i < cpuhw->n_events) { cpuhw->event[i-1] = cpuhw->event[i]; + cpuhw->events[i-1] = cpuhw->events[i]; + cpuhw->flags[i-1] = cpuhw->flags[i]; + } --cpuhw->n_events; ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr); if (event->hw.idx) {