From f39ec2d76a028a470b8fe9a83ecf82d1000a385c Mon Sep 17 00:00:00 2001
From: Mark Salter <msalter@redhat.com>
Date: Sat, 5 Nov 2011 10:57:40 -0400
Subject: [PATCH] --- yaml --- r: 283193 b: refs/heads/master c:
 25b48ff852e2e71b0d44d8ee6f69c9b704bd5070 h: refs/heads/master i:   283191:
 873b1248facbc6c5ba03dc8ac2db1b02650b4bd5 v: v3

---
 [refs]                             |  2 +-
 trunk/arch/c6x/platforms/timer64.c | 10 +++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index 15b7e234a459..3508ee08a890 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 4a059ff3a9a8bd4ee78e3b89721b698ddb43d385
+refs/heads/master: 25b48ff852e2e71b0d44d8ee6f69c9b704bd5070
diff --git a/trunk/arch/c6x/platforms/timer64.c b/trunk/arch/c6x/platforms/timer64.c
index 783415861dae..03c03c249191 100644
--- a/trunk/arch/c6x/platforms/timer64.c
+++ b/trunk/arch/c6x/platforms/timer64.c
@@ -215,9 +215,17 @@ void __init timer64_init(void)
 
 	/* If there is a device state control, save the ID. */
 	err = of_property_read_u32(np, "ti,dscr-dev-enable", &val);
-	if (!err)
+	if (!err) {
 		timer64_devstate_id = val;
 
+		/*
+		 * It is necessary to enable the timer block here because
+		 * the TIMER_DIVISOR macro needs to read a timer register
+		 * to get the divisor.
+		 */
+		dscr_set_devstate(timer64_devstate_id, DSCR_DEVSTATE_ENABLED);
+	}
+
 	pr_debug("%s: Timer irq=%d.\n", np->full_name, cd->irq);
 
 	clockevents_calc_mult_shift(cd, c6x_core_freq / TIMER_DIVISOR, 5);