From f41793ec491adc302e90a842db4bbf2c439cd78d Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Wed, 2 Nov 2011 18:08:25 -0400 Subject: [PATCH] --- yaml --- r: 275008 b: refs/heads/master c: 0e2c978ef2248156f36db7fcda8c7b67998ec58a h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/ni.c | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index a8bbae873a2b..54fa1c0cfe4c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: cf2aff6eff251b6fbdaf8c253e65ff7c693de8cd +refs/heads/master: 0e2c978ef2248156f36db7fcda8c7b67998ec58a diff --git a/trunk/drivers/gpu/drm/radeon/ni.c b/trunk/drivers/gpu/drm/radeon/ni.c index 56afaff6299a..722cfb398992 100644 --- a/trunk/drivers/gpu/drm/radeon/ni.c +++ b/trunk/drivers/gpu/drm/radeon/ni.c @@ -261,8 +261,11 @@ int ni_mc_load_microcode(struct radeon_device *rdev) WREG32(MC_SEQ_SUP_CNTL, 0x00000001); /* wait for training to complete */ - while (!(RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD)) - udelay(10); + for (i = 0; i < rdev->usec_timeout; i++) { + if (RREG32(MC_IO_PAD_CNTL_D0) & MEM_FALL_OUT_CMD) + break; + udelay(1); + } if (running) WREG32(MC_SHARED_BLACKOUT_CNTL, blackout);