From f4266b744703d4ebe60f1a93d1752d72834dca56 Mon Sep 17 00:00:00 2001 From: Paulo Zanoni Date: Fri, 4 May 2012 17:18:22 -0300 Subject: [PATCH] --- yaml --- r: 307413 b: refs/heads/master c: 60c5ea2dd981d929d873823433294b991d3e3cd8 h: refs/heads/master i: 307411: dd3482fa749521a29fd98d6bacbb2c342305f4e1 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 1 + trunk/drivers/gpu/drm/i915/intel_hdmi.c | 3 +++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 00abfc88f3c4..a8bc5df3abf9 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: ecb978515c88183b111b8994acd6b572b1361a72 +refs/heads/master: 60c5ea2dd981d929d873823433294b991d3e3cd8 diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index 71e7af91f1b1..ce6e64dd00ff 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -1711,6 +1711,7 @@ #define VIDEO_DIP_FREQ_ONCE (0 << 16) #define VIDEO_DIP_FREQ_VSYNC (1 << 16) #define VIDEO_DIP_FREQ_2VSYNC (2 << 16) +#define VIDEO_DIP_FREQ_MASK (3 << 16) /* Panel power sequencing */ #define PP_STATUS 0x61200 diff --git a/trunk/drivers/gpu/drm/i915/intel_hdmi.c b/trunk/drivers/gpu/drm/i915/intel_hdmi.c index 6c96bb54e967..4a4ee8b25f2f 100644 --- a/trunk/drivers/gpu/drm/i915/intel_hdmi.c +++ b/trunk/drivers/gpu/drm/i915/intel_hdmi.c @@ -164,6 +164,7 @@ static void i9xx_write_infoframe(struct drm_encoder *encoder, } val |= intel_infoframe_enable(frame); + val &= ~VIDEO_DIP_FREQ_MASK; val |= intel_infoframe_frequency(frame); I915_WRITE(VIDEO_DIP_CTL, val); @@ -203,6 +204,7 @@ static void ironlake_write_infoframe(struct drm_encoder *encoder, } val |= intel_infoframe_enable(frame); + val &= ~VIDEO_DIP_FREQ_MASK; val |= intel_infoframe_frequency(frame); I915_WRITE(reg, val); @@ -236,6 +238,7 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, } val |= intel_infoframe_enable(frame); + val &= ~VIDEO_DIP_FREQ_MASK; val |= intel_infoframe_frequency(frame); I915_WRITE(reg, val);