From f4abeab5c78f9e2501cacbf4ee32cd37a95296a6 Mon Sep 17 00:00:00 2001
From: Andrew Isaacson <adi@broadcom.com>
Date: Wed, 19 Oct 2005 23:54:43 -0700
Subject: [PATCH] --- yaml --- r: 11275 b: refs/heads/master c:
 d121ced21d79eab7726bfe6b1e33da4ae86072c0 h: refs/heads/master i:   11273:
 f919a8149121e6600a56cfd73738329e2b310041   11271:
 9d27ba39f174ef3f4d0810f3342ff250255fed9e v: v3

---
 [refs]                             | 2 +-
 trunk/arch/mips/kernel/cpu-probe.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/[refs] b/[refs]
index db6ba56e8c49..3ccd5794513b 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 485a4a928a059a361c7363e7ce0eab330a09dbd3
+refs/heads/master: d121ced21d79eab7726bfe6b1e33da4ae86072c0
diff --git a/trunk/arch/mips/kernel/cpu-probe.c b/trunk/arch/mips/kernel/cpu-probe.c
index 72c580d94e24..f7a841573b84 100644
--- a/trunk/arch/mips/kernel/cpu-probe.c
+++ b/trunk/arch/mips/kernel/cpu-probe.c
@@ -612,7 +612,7 @@ static inline void cpu_probe_sibyte(struct cpuinfo_mips *c)
 	 * cache code which eventually will be folded into c-r4k.c.  Until
 	 * then we pretend it's got it's own cache architecture.
 	 */
-	c->options &= MIPS_CPU_4K_CACHE;
+	c->options &= ~MIPS_CPU_4K_CACHE;
 	c->options |= MIPS_CPU_SB1_CACHE;
 
 	switch (c->processor_id & 0xff00) {