From f4acefe163bb6a361834735dedb6a9c638bedec0 Mon Sep 17 00:00:00 2001
From: Chris Wilson <chris@chris-wilson.co.uk>
Date: Fri, 3 Dec 2010 21:13:16 +0000
Subject: [PATCH] --- yaml --- r: 228775 b: refs/heads/master c:
 a589b9f429ac0e5bcdebda0f74ee313d39d69b7f h: refs/heads/master i:   228773:
 51631b12d176d86f1b5f52178fcf8d37fcfb92d1   228771:
 b553da459bc773e0765d3fa9c09db44666a4a910   228767:
 96888c20e5bed6f2131ea0a531d3c640db27aefd v: v3

---
 [refs]                                     |  2 +-
 trunk/drivers/gpu/drm/i915/intel_display.c | 10 +++++-----
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/[refs] b/[refs]
index 949186ab18f4..3f43fe0ec62d 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 17fe6981109e995f36723e4880a97d48fa38920a
+refs/heads/master: a589b9f429ac0e5bcdebda0f74ee313d39d69b7f
diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c
index f7962b741c94..e3b8d0dc7a7d 100644
--- a/trunk/drivers/gpu/drm/i915/intel_display.c
+++ b/trunk/drivers/gpu/drm/i915/intel_display.c
@@ -4089,13 +4089,13 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
 			}
 			I915_WRITE(DPLL_MD(pipe), temp);
 		} else {
-			/* write it again -- the BIOS does, after all */
+			/* The pixel multiplier can only be updated once the
+			 * DPLL is enabled and the clocks are stable.
+			 *
+			 * So write it again.
+			 */
 			I915_WRITE(dpll_reg, dpll);
 		}
-
-		/* Wait for the clocks to stabilize. */
-		POSTING_READ(dpll_reg);
-		udelay(150);
 	}
 
 	intel_crtc->lowfreq_avail = false;