From f50ec1b95570a9421f8c12bcefff3fd9584425f5 Mon Sep 17 00:00:00 2001
From: Paul Walmsley <paul@pwsan.com>
Date: Wed, 27 Jun 2012 14:53:46 -0600
Subject: [PATCH] --- yaml --- r: 313026 b: refs/heads/master c:
 82ee620dc6e1906fe064e93047489f0aea72b75b h: refs/heads/master v: v3

---
 [refs]                                          |  2 +-
 trunk/arch/arm/mach-omap2/clock3xxx_data.c      |  8 ++++++--
 .../arch/arm/mach-omap2/omap_hwmod_3xxx_data.c  | 17 +++++++++++++++++
 3 files changed, 24 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index fa7f9797e073..a6db9e72cbc2 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: bf7652372777c3a6003a05a3e9e462c3dcd0c90d
+refs/heads/master: 82ee620dc6e1906fe064e93047489f0aea72b75b
diff --git a/trunk/arch/arm/mach-omap2/clock3xxx_data.c b/trunk/arch/arm/mach-omap2/clock3xxx_data.c
index 58c6e477a4f1..4a3c1c819adc 100644
--- a/trunk/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/trunk/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3201,8 +3201,12 @@ static struct clk vpfe_fck = {
 };
 
 /*
- * The UART1/2 functional clock acts as the functional
- * clock for UART4. No separate fclk control available.
+ * The UART1/2 functional clock acts as the functional clock for
+ * UART4. No separate fclk control available.  XXX Well now we have a
+ * uart4_fck that is apparently used as the UART4 functional clock,
+ * but it also seems that uart1_fck or uart2_fck are still needed, at
+ * least for UART4 softresets to complete.  This really needs
+ * clarification.
  */
 static struct clk uart4_ick_am35xx = {
 	.name		= "uart4_ick",
diff --git a/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 2f4889e514e5..1120d388eca3 100644
--- a/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/trunk/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -536,6 +536,20 @@ static struct omap_hwmod_dma_info am35xx_uart4_sdma_reqs[] = {
 	{ .dma_req = -1 }
 };
 
+/*
+ * XXX AM35xx UART4 cannot complete its softreset without uart1_fck or
+ * uart2_fck being enabled.  So we add uart1_fck as an optional clock,
+ * below, and set the HWMOD_CONTROL_OPT_CLKS_IN_RESET.  This really
+ * should not be needed.  The functional clock structure of the AM35xx
+ * UART4 is extremely unclear and opaque; it is unclear what the role
+ * of uart1/2_fck is for the UART4.  Any clarification from either
+ * empirical testing or the AM3505/3517 hardware designers would be
+ * most welcome.
+ */
+static struct omap_hwmod_opt_clk am35xx_uart4_opt_clks[] = {
+	{ .role = "softreset_uart1_fck", .clk = "uart1_fck" },
+};
+
 static struct omap_hwmod am35xx_uart4_hwmod = {
 	.name		= "uart4",
 	.mpu_irqs	= am35xx_uart4_mpu_irqs,
@@ -550,6 +564,9 @@ static struct omap_hwmod am35xx_uart4_hwmod = {
 			.idlest_idle_bit = AM35XX_ST_UART4_SHIFT,
 		},
 	},
+	.opt_clks	= am35xx_uart4_opt_clks,
+	.opt_clks_cnt	= ARRAY_SIZE(am35xx_uart4_opt_clks),
+	.flags		= HWMOD_CONTROL_OPT_CLKS_IN_RESET,
 	.class		= &omap2_uart_class,
 };