From f6b5ef2c92a48a66bfde14d6a3097ad535c9bcdc Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michel=20D=C3=A4nzer?= Date: Fri, 26 Mar 2010 19:18:55 +0000 Subject: [PATCH] --- yaml --- r: 189360 b: refs/heads/master c: 3ca82da3ebe019facd611184385897fa614e6b9e h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/radeon_object.c | 6 ++++-- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/[refs] b/[refs] index 333ae594c53d..f051816f8f66 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: b8c40d6269d5e515341599b2e395f2dab4490d74 +refs/heads/master: 3ca82da3ebe019facd611184385897fa614e6b9e diff --git a/trunk/drivers/gpu/drm/radeon/radeon_object.c b/trunk/drivers/gpu/drm/radeon/radeon_object.c index fc9d00ac6b15..dc7e3f449138 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_object.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_object.c @@ -185,8 +185,10 @@ int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) return 0; } radeon_ttm_placement_from_domain(bo, domain); - /* force to pin into visible video ram */ - bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; + if (domain == RADEON_GEM_DOMAIN_VRAM) { + /* force to pin into visible video ram */ + bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; + } for (i = 0; i < bo->placement.num_placement; i++) bo->placements[i] |= TTM_PL_FLAG_NO_EVICT; r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);