From f6ba1b5ea51bb139792c929e6159f75ba4cad59f Mon Sep 17 00:00:00 2001
From: Lennert Buytenhek <buytenh@wantstofly.org>
Date: Mon, 18 Dec 2006 01:04:09 +0100
Subject: [PATCH] --- yaml --- r: 44699 b: refs/heads/master c:
 c041ffb36407897bbc3b7bf87d1fa856ce085cdf h: refs/heads/master i:   44697:
 e7259c1cf2364d132b70499493f3ecf05cfdfc40   44695:
 888434109d9acf9d8f508538cbd07d65cea0e8d6 v: v3

---
 [refs]                                      |  2 +-
 trunk/include/asm-arm/arch-ixp23xx/memory.h | 16 +---------------
 2 files changed, 2 insertions(+), 16 deletions(-)

diff --git a/[refs] b/[refs]
index ab74e137d4a3..33ef4470bc6d 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: ab9d90db956dec1a83f4c4ef443df6bdbfc3f25d
+refs/heads/master: c041ffb36407897bbc3b7bf87d1fa856ce085cdf
diff --git a/trunk/include/asm-arm/arch-ixp23xx/memory.h b/trunk/include/asm-arm/arch-ixp23xx/memory.h
index c85fc06a043c..6d859d742d7f 100644
--- a/trunk/include/asm-arm/arch-ixp23xx/memory.h
+++ b/trunk/include/asm-arm/arch-ixp23xx/memory.h
@@ -41,21 +41,7 @@
 	data = *((volatile int *)IXP23XX_PCI_SDRAM_BAR);		\
 	 __phys_to_virt((((b - (data & 0xfffffff0)) + 0x00000000))); })
 
-/*
- * Coherency support.  Only supported on A2 CPUs or on A1
- * systems that have the cache coherency workaround.
- */
-static inline int __ixp23xx_arch_is_coherent(void)
-{
-	extern unsigned int processor_id;
-
-	if (((processor_id & 15) >= 4) || machine_is_roadrunner())
-		return 1;
-
-	return 0;
-}
-
-#define arch_is_coherent()	__ixp23xx_arch_is_coherent()
+#define arch_is_coherent()	1
 
 #endif