From f72e046cc00c8ccb0f63bbcd05de4126e7fff6aa Mon Sep 17 00:00:00 2001 From: Timur Tabi Date: Tue, 16 Oct 2012 17:33:49 -0500 Subject: [PATCH] --- yaml --- r: 344530 b: refs/heads/master c: ceb001b077af64b20a8027132cfe015c80f4319d h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/video/fsl-diu-fb.c | 23 +++++++++++++++-------- 2 files changed, 16 insertions(+), 9 deletions(-) diff --git a/[refs] b/[refs] index 1500647595be..378b88f0738f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 7af3b136d4e035d71c4e70c4b4a2017a10623fc0 +refs/heads/master: ceb001b077af64b20a8027132cfe015c80f4319d diff --git a/trunk/drivers/video/fsl-diu-fb.c b/trunk/drivers/video/fsl-diu-fb.c index 37175ac6584a..0883bc42cd5a 100644 --- a/trunk/drivers/video/fsl-diu-fb.c +++ b/trunk/drivers/video/fsl-diu-fb.c @@ -825,12 +825,8 @@ static void update_lcdc(struct fb_info *info) out_be32(&hw->gamma, DMA_ADDR(data, gamma)); out_be32(&hw->cursor, DMA_ADDR(data, cursor)); - out_be32(&hw->bgnd, 0x007F7F7F); /* BGND */ - out_be32(&hw->bgnd_wb, 0); /* BGND_WB */ - out_be32(&hw->disp_size, (var->yres << 16 | var->xres)); - /* DISP SIZE */ - out_be32(&hw->wb_size, 0); /* WB SIZE */ - out_be32(&hw->wb_mem_addr, 0); /* WB MEM ADDR */ + out_be32(&hw->bgnd, 0x007F7F7F); /* Set background to grey */ + out_be32(&hw->disp_size, (var->yres << 16) | var->xres); /* Horizontal and vertical configuration register */ temp = var->left_margin << 22 | /* BP_H */ @@ -847,9 +843,20 @@ static void update_lcdc(struct fb_info *info) diu_ops.set_pixel_clock(var->pixclock); - out_be32(&hw->syn_pol, 0); /* SYNC SIGNALS POLARITY */ - out_be32(&hw->int_status, 0); /* INTERRUPT STATUS */ +#ifndef CONFIG_PPC_MPC512x + /* + * The PLUT register is defined differently on the MPC5121 than it + * is on other SOCs. Unfortunately, there's no documentation that + * explains how it's supposed to be programmed, so for now, we leave + * it at the default value on the MPC5121. + * + * For other SOCs, program it for the highest priority, which will + * reduce the chance of underrun. Technically, we should scale the + * priority to match the screen resolution, but doing that properly + * requires delicate fine-tuning for each use-case. + */ out_be32(&hw->plut, 0x01F5F666); +#endif /* Enable the DIU */ enable_lcdc(info);