From f84caaf25a7c4eb96fef05fec100d941c4559c01 Mon Sep 17 00:00:00 2001
From: Roland Vossen <rvossen@broadcom.com>
Date: Tue, 13 Sep 2011 09:49:49 +0200
Subject: [PATCH] --- yaml --- r: 268416 b: refs/heads/master c:
 5b876618c0ce69151571f6f197e7c54fd5b80081 h: refs/heads/master v: v3

---
 [refs]                                         | 2 +-
 trunk/drivers/staging/brcm80211/brcmsmac/dma.c | 8 ++++++--
 2 files changed, 7 insertions(+), 3 deletions(-)

diff --git a/[refs] b/[refs]
index d8c72a8dacfe..8ddb718902ad 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: 7d9e0b9a7f47844f3147db90d2149caf32dbf5e9
+refs/heads/master: 5b876618c0ce69151571f6f197e7c54fd5b80081
diff --git a/trunk/drivers/staging/brcm80211/brcmsmac/dma.c b/trunk/drivers/staging/brcm80211/brcmsmac/dma.c
index 6c9b1fe29e9b..06990b3d6cde 100644
--- a/trunk/drivers/staging/brcm80211/brcmsmac/dma.c
+++ b/trunk/drivers/staging/brcm80211/brcmsmac/dma.c
@@ -24,8 +24,8 @@
 #include "dma.h"
 
 /*
- * Each descriptor ring must be 8kB aligned, and fit within a
- * contiguous 8kB physical address.
+ * DMA hardware requires each descriptor ring to be 8kB aligned, and fit within
+ * a contiguous 8kB physical address.
  */
 #define D64RINGALIGN_BITS	13
 #define	D64MAXRINGSZ		(1 << D64RINGALIGN_BITS)
@@ -440,6 +440,10 @@ static bool _dma_descriptor_align(struct dma_info *di)
 	return true;
 }
 
+/*
+ * Descriptor table must start at the DMA hardware dictated alignment, so
+ * allocated memory must be large enough to support this requirement.
+ */
 static void *dma_alloc_consistent(struct pci_dev *pdev, uint size,
 				  u16 align_bits, uint *alloced,
 				  dma_addr_t *pap)