From f8e686f1535b196f57b6ff796b128fe76a0d9d4f Mon Sep 17 00:00:00 2001 From: Scott Wood Date: Mon, 25 Jun 2007 14:50:41 -0500 Subject: [PATCH] --- yaml --- r: 67479 b: refs/heads/master c: 7401685242fbcbf4b0660726372c77a88c4af17d h: refs/heads/master i: 67477: b4b7c390dfa6fd6aae8029279a48d0799cb5e1f7 67475: 5172ed0332e8146b07623f7d3068f66a974add64 67471: 4734c75c7ab408f639aab9b84fb60474b89c5ab1 v: v3 --- [refs] | 2 +- trunk/arch/powerpc/kernel/head_8xx.S | 6 ++++++ trunk/arch/powerpc/platforms/8xx/Kconfig | 16 ++++++++++++++++ 3 files changed, 23 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 6aaf9e5ee80c..55676289161f 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 663edbd2640447dc43840568cd5701e6c9878d63 +refs/heads/master: 7401685242fbcbf4b0660726372c77a88c4af17d diff --git a/trunk/arch/powerpc/kernel/head_8xx.S b/trunk/arch/powerpc/kernel/head_8xx.S index 9c30938aad52..f7458396cd7c 100644 --- a/trunk/arch/powerpc/kernel/head_8xx.S +++ b/trunk/arch/powerpc/kernel/head_8xx.S @@ -298,6 +298,12 @@ InstructionTLBMiss: stw r10, 0(r0) stw r11, 4(r0) mfspr r10, SPRN_SRR0 /* Get effective address of fault */ +#ifdef CONFIG_8xx_CPU15 + addi r11, r10, 0x1000 + tlbie r11 + addi r11, r10, -0x1000 + tlbie r11 +#endif DO_8xx_CPU6(0x3780, r3) mtspr SPRN_MD_EPN, r10 /* Have to use MD_EPN for walk, MI_EPN can't */ mfspr r10, SPRN_M_TWB /* Get level 1 table entry address */ diff --git a/trunk/arch/powerpc/platforms/8xx/Kconfig b/trunk/arch/powerpc/platforms/8xx/Kconfig index 8ecd01ad0de8..322b155f24ec 100644 --- a/trunk/arch/powerpc/platforms/8xx/Kconfig +++ b/trunk/arch/powerpc/platforms/8xx/Kconfig @@ -100,6 +100,22 @@ config 8xx_CPU6 If in doubt, say N here. +config 8xx_CPU15 + bool "CPU15 Silicon Errata" + default y + help + This enables a workaround for erratum CPU15 on MPC8xx chips. + This bug can cause incorrect code execution under certain + circumstances. This workaround adds some overhead (a TLB miss + every time execution crosses a page boundary), and you may wish + to disable it if you have worked around the bug in the compiler + (by not placing conditional branches or branches to LR or CTR + in the last word of a page, with a target of the last cache + line in the next page), or if you have used some other + workaround. + + If in doubt, say Y here. + choice prompt "Microcode patch selection" default NO_UCODE_PATCH