From f9885ae511e19d1d1940a0db61f1f03c3b0d7d23 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Mon, 18 Jan 2010 07:21:41 +0000 Subject: [PATCH] --- yaml --- r: 185807 b: refs/heads/master c: 23d874054663efaf18340dc554df1b935820cbab h: refs/heads/master i: 185805: 487c1f875d76101f3bd2f4214e921be2b9012b2d 185803: 23b40b8cf03d67a60a1d2bd5ad906c39c3bf5343 185799: 5648ed5fe874dfb285ca7da78ed091e5433d761f 185791: fd6da42913ceb57a711df62def52458283711389 v: v3 --- [refs] | 2 +- trunk/drivers/ide/cmd64x.c | 17 ++++++++++------- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/[refs] b/[refs] index e5a9d7bdaca3..e49654950101 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f6d23c2e2e398dc96c58494be2934f0c11285e3a +refs/heads/master: 23d874054663efaf18340dc554df1b935820cbab diff --git a/trunk/drivers/ide/cmd64x.c b/trunk/drivers/ide/cmd64x.c index a65a69171250..5f80312e636b 100644 --- a/trunk/drivers/ide/cmd64x.c +++ b/trunk/drivers/ide/cmd64x.c @@ -88,9 +88,6 @@ static void cmd64x_program_timings(ide_drive_t *drive, u8 mode) pci_write_config_byte(dev, drwtim_regs[drive->dn], (t.active << 4) | t.recover); - if (mode >= XFER_SW_DMA_0) - return; - /* * The primary channel has individual address setup timing registers * for each drive and the hardware selects the slowest timing itself. @@ -100,11 +97,17 @@ static void cmd64x_program_timings(ide_drive_t *drive, u8 mode) if (hwif->channel) { ide_drive_t *pair = ide_get_pair_dev(drive); - ide_set_drivedata(drive, (void *)(unsigned long)t.setup); + if (pair) { + struct ide_timing tp; - if (pair) - t.setup = max_t(u8, t.setup, - (unsigned long)ide_get_drivedata(pair)); + ide_timing_compute(pair, pair->pio_mode, &tp, T, 0); + ide_timing_merge(&t, &tp, &t, IDE_TIMING_SETUP); + if (pair->dma_mode) { + ide_timing_compute(pair, pair->dma_mode, + &tp, T, 0); + ide_timing_merge(&tp, &t, &t, IDE_TIMING_SETUP); + } + } } if (t.setup > 5) /* shouldn't actually happen... */