diff --git a/[refs] b/[refs]
index 678d9a5ab496..ab8b91acd0a6 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
---
-refs/heads/master: 150a8dcf109f68f322bf112c7604f2d950303f00
+refs/heads/master: 0d5cadb87e0fa764db7fa0b78d8a6f173cb475a1
diff --git a/trunk/Documentation/DocBook/writing-an-alsa-driver.tmpl b/trunk/Documentation/DocBook/writing-an-alsa-driver.tmpl
index 06741e925985..bd6fee22c4dd 100644
--- a/trunk/Documentation/DocBook/writing-an-alsa-driver.tmpl
+++ b/trunk/Documentation/DocBook/writing-an-alsa-driver.tmpl
@@ -6164,12 +6164,14 @@ struct _snd_pcm_runtime {
The macro takes an conditional expression to evaluate.
- When CONFIG_SND_DEBUG, is set, if the
- expression is non-zero, it shows the warning message such as
+ When CONFIG_SND_DEBUG, is set, the
+ expression is actually evaluated. If it's non-zero, it shows
+ the warning message such as
BUG? (xxx)
- normally followed by stack trace.
-
- In both cases it returns the evaluated value.
+ normally followed by stack trace. It returns the evaluated
+ value.
+ When no CONFIG_SND_DEBUG is set, this
+ macro always returns zero.
diff --git a/trunk/Documentation/EDID/1600x1200.S b/trunk/Documentation/EDID/1600x1200.S
deleted file mode 100644
index 0ded64cfd1f5..000000000000
--- a/trunk/Documentation/EDID/1600x1200.S
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- 1600x1200.S: EDID data set for standard 1600x1200 60 Hz monitor
-
- Copyright (C) 2013 Carsten Emde
-
- This program is free software; you can redistribute it and/or
- modify it under the terms of the GNU General Public License
- as published by the Free Software Foundation; either version 2
- of the License, or (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
-*/
-
-/* EDID */
-#define VERSION 1
-#define REVISION 3
-
-/* Display */
-#define CLOCK 162000 /* kHz */
-#define XPIX 1600
-#define YPIX 1200
-#define XY_RATIO XY_RATIO_4_3
-#define XBLANK 560
-#define YBLANK 50
-#define XOFFSET 64
-#define XPULSE 192
-#define YOFFSET (63+1)
-#define YPULSE (63+3)
-#define DPI 72
-#define VFREQ 60 /* Hz */
-#define TIMING_NAME "Linux UXGA"
-#define ESTABLISHED_TIMINGS_BITS 0x00 /* none */
-#define HSYNC_POL 1
-#define VSYNC_POL 1
-#define CRC 0x9d
-
-#include "edid.S"
diff --git a/trunk/Documentation/EDID/HOWTO.txt b/trunk/Documentation/EDID/HOWTO.txt
index 7146db1d9e8c..2d0a8f09475d 100644
--- a/trunk/Documentation/EDID/HOWTO.txt
+++ b/trunk/Documentation/EDID/HOWTO.txt
@@ -18,12 +18,12 @@ CONFIG_DRM_LOAD_EDID_FIRMWARE was introduced. It allows to provide an
individually prepared or corrected EDID data set in the /lib/firmware
directory from where it is loaded via the firmware interface. The code
(see drivers/gpu/drm/drm_edid_load.c) contains built-in data sets for
-commonly used screen resolutions (1024x768, 1280x1024, 1600x1200,
-1680x1050, 1920x1080) as binary blobs, but the kernel source tree does
-not contain code to create these data. In order to elucidate the origin
-of the built-in binary EDID blobs and to facilitate the creation of
-individual data for a specific misbehaving monitor, commented sources
-and a Makefile environment are given here.
+commonly used screen resolutions (1024x768, 1280x1024, 1680x1050,
+1920x1080) as binary blobs, but the kernel source tree does not contain
+code to create these data. In order to elucidate the origin of the
+built-in binary EDID blobs and to facilitate the creation of individual
+data for a specific misbehaving monitor, commented sources and a
+Makefile environment are given here.
To create binary EDID and C source code files from the existing data
material, simply type "make".
diff --git a/trunk/Documentation/arm/cluster-pm-race-avoidance.txt b/trunk/Documentation/arm/cluster-pm-race-avoidance.txt
deleted file mode 100644
index 750b6fc24af9..000000000000
--- a/trunk/Documentation/arm/cluster-pm-race-avoidance.txt
+++ /dev/null
@@ -1,498 +0,0 @@
-Cluster-wide Power-up/power-down race avoidance algorithm
-=========================================================
-
-This file documents the algorithm which is used to coordinate CPU and
-cluster setup and teardown operations and to manage hardware coherency
-controls safely.
-
-The section "Rationale" explains what the algorithm is for and why it is
-needed. "Basic model" explains general concepts using a simplified view
-of the system. The other sections explain the actual details of the
-algorithm in use.
-
-
-Rationale
----------
-
-In a system containing multiple CPUs, it is desirable to have the
-ability to turn off individual CPUs when the system is idle, reducing
-power consumption and thermal dissipation.
-
-In a system containing multiple clusters of CPUs, it is also desirable
-to have the ability to turn off entire clusters.
-
-Turning entire clusters off and on is a risky business, because it
-involves performing potentially destructive operations affecting a group
-of independently running CPUs, while the OS continues to run. This
-means that we need some coordination in order to ensure that critical
-cluster-level operations are only performed when it is truly safe to do
-so.
-
-Simple locking may not be sufficient to solve this problem, because
-mechanisms like Linux spinlocks may rely on coherency mechanisms which
-are not immediately enabled when a cluster powers up. Since enabling or
-disabling those mechanisms may itself be a non-atomic operation (such as
-writing some hardware registers and invalidating large caches), other
-methods of coordination are required in order to guarantee safe
-power-down and power-up at the cluster level.
-
-The mechanism presented in this document describes a coherent memory
-based protocol for performing the needed coordination. It aims to be as
-lightweight as possible, while providing the required safety properties.
-
-
-Basic model
------------
-
-Each cluster and CPU is assigned a state, as follows:
-
- DOWN
- COMING_UP
- UP
- GOING_DOWN
-
- +---------> UP ----------+
- | v
-
- COMING_UP GOING_DOWN
-
- ^ |
- +--------- DOWN <--------+
-
-
-DOWN: The CPU or cluster is not coherent, and is either powered off or
- suspended, or is ready to be powered off or suspended.
-
-COMING_UP: The CPU or cluster has committed to moving to the UP state.
- It may be part way through the process of initialisation and
- enabling coherency.
-
-UP: The CPU or cluster is active and coherent at the hardware
- level. A CPU in this state is not necessarily being used
- actively by the kernel.
-
-GOING_DOWN: The CPU or cluster has committed to moving to the DOWN
- state. It may be part way through the process of teardown and
- coherency exit.
-
-
-Each CPU has one of these states assigned to it at any point in time.
-The CPU states are described in the "CPU state" section, below.
-
-Each cluster is also assigned a state, but it is necessary to split the
-state value into two parts (the "cluster" state and "inbound" state) and
-to introduce additional states in order to avoid races between different
-CPUs in the cluster simultaneously modifying the state. The cluster-
-level states are described in the "Cluster state" section.
-
-To help distinguish the CPU states from cluster states in this
-discussion, the state names are given a CPU_ prefix for the CPU states,
-and a CLUSTER_ or INBOUND_ prefix for the cluster states.
-
-
-CPU state
----------
-
-In this algorithm, each individual core in a multi-core processor is
-referred to as a "CPU". CPUs are assumed to be single-threaded:
-therefore, a CPU can only be doing one thing at a single point in time.
-
-This means that CPUs fit the basic model closely.
-
-The algorithm defines the following states for each CPU in the system:
-
- CPU_DOWN
- CPU_COMING_UP
- CPU_UP
- CPU_GOING_DOWN
-
- cluster setup and
- CPU setup complete policy decision
- +-----------> CPU_UP ------------+
- | v
-
- CPU_COMING_UP CPU_GOING_DOWN
-
- ^ |
- +----------- CPU_DOWN <----------+
- policy decision CPU teardown complete
- or hardware event
-
-
-The definitions of the four states correspond closely to the states of
-the basic model.
-
-Transitions between states occur as follows.
-
-A trigger event (spontaneous) means that the CPU can transition to the
-next state as a result of making local progress only, with no
-requirement for any external event to happen.
-
-
-CPU_DOWN:
-
- A CPU reaches the CPU_DOWN state when it is ready for
- power-down. On reaching this state, the CPU will typically
- power itself down or suspend itself, via a WFI instruction or a
- firmware call.
-
- Next state: CPU_COMING_UP
- Conditions: none
-
- Trigger events:
-
- a) an explicit hardware power-up operation, resulting
- from a policy decision on another CPU;
-
- b) a hardware event, such as an interrupt.
-
-
-CPU_COMING_UP:
-
- A CPU cannot start participating in hardware coherency until the
- cluster is set up and coherent. If the cluster is not ready,
- then the CPU will wait in the CPU_COMING_UP state until the
- cluster has been set up.
-
- Next state: CPU_UP
- Conditions: The CPU's parent cluster must be in CLUSTER_UP.
- Trigger events: Transition of the parent cluster to CLUSTER_UP.
-
- Refer to the "Cluster state" section for a description of the
- CLUSTER_UP state.
-
-
-CPU_UP:
- When a CPU reaches the CPU_UP state, it is safe for the CPU to
- start participating in local coherency.
-
- This is done by jumping to the kernel's CPU resume code.
-
- Note that the definition of this state is slightly different
- from the basic model definition: CPU_UP does not mean that the
- CPU is coherent yet, but it does mean that it is safe to resume
- the kernel. The kernel handles the rest of the resume
- procedure, so the remaining steps are not visible as part of the
- race avoidance algorithm.
-
- The CPU remains in this state until an explicit policy decision
- is made to shut down or suspend the CPU.
-
- Next state: CPU_GOING_DOWN
- Conditions: none
- Trigger events: explicit policy decision
-
-
-CPU_GOING_DOWN:
-
- While in this state, the CPU exits coherency, including any
- operations required to achieve this (such as cleaning data
- caches).
-
- Next state: CPU_DOWN
- Conditions: local CPU teardown complete
- Trigger events: (spontaneous)
-
-
-Cluster state
--------------
-
-A cluster is a group of connected CPUs with some common resources.
-Because a cluster contains multiple CPUs, it can be doing multiple
-things at the same time. This has some implications. In particular, a
-CPU can start up while another CPU is tearing the cluster down.
-
-In this discussion, the "outbound side" is the view of the cluster state
-as seen by a CPU tearing the cluster down. The "inbound side" is the
-view of the cluster state as seen by a CPU setting the CPU up.
-
-In order to enable safe coordination in such situations, it is important
-that a CPU which is setting up the cluster can advertise its state
-independently of the CPU which is tearing down the cluster. For this
-reason, the cluster state is split into two parts:
-
- "cluster" state: The global state of the cluster; or the state
- on the outbound side:
-
- CLUSTER_DOWN
- CLUSTER_UP
- CLUSTER_GOING_DOWN
-
- "inbound" state: The state of the cluster on the inbound side.
-
- INBOUND_NOT_COMING_UP
- INBOUND_COMING_UP
-
-
- The different pairings of these states results in six possible
- states for the cluster as a whole:
-
- CLUSTER_UP
- +==========> INBOUND_NOT_COMING_UP -------------+
- # |
- |
- CLUSTER_UP <----+ |
- INBOUND_COMING_UP | v
-
- ^ CLUSTER_GOING_DOWN CLUSTER_GOING_DOWN
- # INBOUND_COMING_UP <=== INBOUND_NOT_COMING_UP
-
- CLUSTER_DOWN | |
- INBOUND_COMING_UP <----+ |
- |
- ^ |
- +=========== CLUSTER_DOWN <------------+
- INBOUND_NOT_COMING_UP
-
- Transitions -----> can only be made by the outbound CPU, and
- only involve changes to the "cluster" state.
-
- Transitions ===##> can only be made by the inbound CPU, and only
- involve changes to the "inbound" state, except where there is no
- further transition possible on the outbound side (i.e., the
- outbound CPU has put the cluster into the CLUSTER_DOWN state).
-
- The race avoidance algorithm does not provide a way to determine
- which exact CPUs within the cluster play these roles. This must
- be decided in advance by some other means. Refer to the section
- "Last man and first man selection" for more explanation.
-
-
- CLUSTER_DOWN/INBOUND_NOT_COMING_UP is the only state where the
- cluster can actually be powered down.
-
- The parallelism of the inbound and outbound CPUs is observed by
- the existence of two different paths from CLUSTER_GOING_DOWN/
- INBOUND_NOT_COMING_UP (corresponding to GOING_DOWN in the basic
- model) to CLUSTER_DOWN/INBOUND_COMING_UP (corresponding to
- COMING_UP in the basic model). The second path avoids cluster
- teardown completely.
-
- CLUSTER_UP/INBOUND_COMING_UP is equivalent to UP in the basic
- model. The final transition to CLUSTER_UP/INBOUND_NOT_COMING_UP
- is trivial and merely resets the state machine ready for the
- next cycle.
-
- Details of the allowable transitions follow.
-
- The next state in each case is notated
-
- / ()
-
- where the is the side on which the transition
- can occur; either the inbound or the outbound side.
-
-
-CLUSTER_DOWN/INBOUND_NOT_COMING_UP:
-
- Next state: CLUSTER_DOWN/INBOUND_COMING_UP (inbound)
- Conditions: none
- Trigger events:
-
- a) an explicit hardware power-up operation, resulting
- from a policy decision on another CPU;
-
- b) a hardware event, such as an interrupt.
-
-
-CLUSTER_DOWN/INBOUND_COMING_UP:
-
- In this state, an inbound CPU sets up the cluster, including
- enabling of hardware coherency at the cluster level and any
- other operations (such as cache invalidation) which are required
- in order to achieve this.
-
- The purpose of this state is to do sufficient cluster-level
- setup to enable other CPUs in the cluster to enter coherency
- safely.
-
- Next state: CLUSTER_UP/INBOUND_COMING_UP (inbound)
- Conditions: cluster-level setup and hardware coherency complete
- Trigger events: (spontaneous)
-
-
-CLUSTER_UP/INBOUND_COMING_UP:
-
- Cluster-level setup is complete and hardware coherency is
- enabled for the cluster. Other CPUs in the cluster can safely
- enter coherency.
-
- This is a transient state, leading immediately to
- CLUSTER_UP/INBOUND_NOT_COMING_UP. All other CPUs on the cluster
- should consider treat these two states as equivalent.
-
- Next state: CLUSTER_UP/INBOUND_NOT_COMING_UP (inbound)
- Conditions: none
- Trigger events: (spontaneous)
-
-
-CLUSTER_UP/INBOUND_NOT_COMING_UP:
-
- Cluster-level setup is complete and hardware coherency is
- enabled for the cluster. Other CPUs in the cluster can safely
- enter coherency.
-
- The cluster will remain in this state until a policy decision is
- made to power the cluster down.
-
- Next state: CLUSTER_GOING_DOWN/INBOUND_NOT_COMING_UP (outbound)
- Conditions: none
- Trigger events: policy decision to power down the cluster
-
-
-CLUSTER_GOING_DOWN/INBOUND_NOT_COMING_UP:
-
- An outbound CPU is tearing the cluster down. The selected CPU
- must wait in this state until all CPUs in the cluster are in the
- CPU_DOWN state.
-
- When all CPUs are in the CPU_DOWN state, the cluster can be torn
- down, for example by cleaning data caches and exiting
- cluster-level coherency.
-
- To avoid wasteful unnecessary teardown operations, the outbound
- should check the inbound cluster state for asynchronous
- transitions to INBOUND_COMING_UP. Alternatively, individual
- CPUs can be checked for entry into CPU_COMING_UP or CPU_UP.
-
-
- Next states:
-
- CLUSTER_DOWN/INBOUND_NOT_COMING_UP (outbound)
- Conditions: cluster torn down and ready to power off
- Trigger events: (spontaneous)
-
- CLUSTER_GOING_DOWN/INBOUND_COMING_UP (inbound)
- Conditions: none
- Trigger events:
-
- a) an explicit hardware power-up operation,
- resulting from a policy decision on another
- CPU;
-
- b) a hardware event, such as an interrupt.
-
-
-CLUSTER_GOING_DOWN/INBOUND_COMING_UP:
-
- The cluster is (or was) being torn down, but another CPU has
- come online in the meantime and is trying to set up the cluster
- again.
-
- If the outbound CPU observes this state, it has two choices:
-
- a) back out of teardown, restoring the cluster to the
- CLUSTER_UP state;
-
- b) finish tearing the cluster down and put the cluster
- in the CLUSTER_DOWN state; the inbound CPU will
- set up the cluster again from there.
-
- Choice (a) permits the removal of some latency by avoiding
- unnecessary teardown and setup operations in situations where
- the cluster is not really going to be powered down.
-
-
- Next states:
-
- CLUSTER_UP/INBOUND_COMING_UP (outbound)
- Conditions: cluster-level setup and hardware
- coherency complete
- Trigger events: (spontaneous)
-
- CLUSTER_DOWN/INBOUND_COMING_UP (outbound)
- Conditions: cluster torn down and ready to power off
- Trigger events: (spontaneous)
-
-
-Last man and First man selection
---------------------------------
-
-The CPU which performs cluster tear-down operations on the outbound side
-is commonly referred to as the "last man".
-
-The CPU which performs cluster setup on the inbound side is commonly
-referred to as the "first man".
-
-The race avoidance algorithm documented above does not provide a
-mechanism to choose which CPUs should play these roles.
-
-
-Last man:
-
-When shutting down the cluster, all the CPUs involved are initially
-executing Linux and hence coherent. Therefore, ordinary spinlocks can
-be used to select a last man safely, before the CPUs become
-non-coherent.
-
-
-First man:
-
-Because CPUs may power up asynchronously in response to external wake-up
-events, a dynamic mechanism is needed to make sure that only one CPU
-attempts to play the first man role and do the cluster-level
-initialisation: any other CPUs must wait for this to complete before
-proceeding.
-
-Cluster-level initialisation may involve actions such as configuring
-coherency controls in the bus fabric.
-
-The current implementation in mcpm_head.S uses a separate mutual exclusion
-mechanism to do this arbitration. This mechanism is documented in
-detail in vlocks.txt.
-
-
-Features and Limitations
-------------------------
-
-Implementation:
-
- The current ARM-based implementation is split between
- arch/arm/common/mcpm_head.S (low-level inbound CPU operations) and
- arch/arm/common/mcpm_entry.c (everything else):
-
- __mcpm_cpu_going_down() signals the transition of a CPU to the
- CPU_GOING_DOWN state.
-
- __mcpm_cpu_down() signals the transition of a CPU to the CPU_DOWN
- state.
-
- A CPU transitions to CPU_COMING_UP and then to CPU_UP via the
- low-level power-up code in mcpm_head.S. This could
- involve CPU-specific setup code, but in the current
- implementation it does not.
-
- __mcpm_outbound_enter_critical() and __mcpm_outbound_leave_critical()
- handle transitions from CLUSTER_UP to CLUSTER_GOING_DOWN
- and from there to CLUSTER_DOWN or back to CLUSTER_UP (in
- the case of an aborted cluster power-down).
-
- These functions are more complex than the __mcpm_cpu_*()
- functions due to the extra inter-CPU coordination which
- is needed for safe transitions at the cluster level.
-
- A cluster transitions from CLUSTER_DOWN back to CLUSTER_UP via
- the low-level power-up code in mcpm_head.S. This
- typically involves platform-specific setup code,
- provided by the platform-specific power_up_setup
- function registered via mcpm_sync_init.
-
-Deep topologies:
-
- As currently described and implemented, the algorithm does not
- support CPU topologies involving more than two levels (i.e.,
- clusters of clusters are not supported). The algorithm could be
- extended by replicating the cluster-level states for the
- additional topological levels, and modifying the transition
- rules for the intermediate (non-outermost) cluster levels.
-
-
-Colophon
---------
-
-Originally created and documented by Dave Martin for Linaro Limited, in
-collaboration with Nicolas Pitre and Achin Gupta.
-
-Copyright (C) 2012-2013 Linaro Limited
-Distributed under the terms of Version 2 of the GNU General Public
-License, as defined in linux/COPYING.
diff --git a/trunk/Documentation/arm/firmware.txt b/trunk/Documentation/arm/firmware.txt
deleted file mode 100644
index c2e468fe7b0b..000000000000
--- a/trunk/Documentation/arm/firmware.txt
+++ /dev/null
@@ -1,88 +0,0 @@
-Interface for registering and calling firmware-specific operations for ARM.
-----
-Written by Tomasz Figa
-
-Some boards are running with secure firmware running in TrustZone secure
-world, which changes the way some things have to be initialized. This makes
-a need to provide an interface for such platforms to specify available firmware
-operations and call them when needed.
-
-Firmware operations can be specified using struct firmware_ops
-
- struct firmware_ops {
- /*
- * Enters CPU idle mode
- */
- int (*do_idle)(void);
- /*
- * Sets boot address of specified physical CPU
- */
- int (*set_cpu_boot_addr)(int cpu, unsigned long boot_addr);
- /*
- * Boots specified physical CPU
- */
- int (*cpu_boot)(int cpu);
- /*
- * Initializes L2 cache
- */
- int (*l2x0_init)(void);
- };
-
-and then registered with register_firmware_ops function
-
- void register_firmware_ops(const struct firmware_ops *ops)
-
-the ops pointer must be non-NULL.
-
-There is a default, empty set of operations provided, so there is no need to
-set anything if platform does not require firmware operations.
-
-To call a firmware operation, a helper macro is provided
-
- #define call_firmware_op(op, ...) \
- ((firmware_ops->op) ? firmware_ops->op(__VA_ARGS__) : (-ENOSYS))
-
-the macro checks if the operation is provided and calls it or otherwise returns
--ENOSYS to signal that given operation is not available (for example, to allow
-fallback to legacy operation).
-
-Example of registering firmware operations:
-
- /* board file */
-
- static int platformX_do_idle(void)
- {
- /* tell platformX firmware to enter idle */
- return 0;
- }
-
- static int platformX_cpu_boot(int i)
- {
- /* tell platformX firmware to boot CPU i */
- return 0;
- }
-
- static const struct firmware_ops platformX_firmware_ops = {
- .do_idle = exynos_do_idle,
- .cpu_boot = exynos_cpu_boot,
- /* other operations not available on platformX */
- };
-
- /* init_early callback of machine descriptor */
- static void __init board_init_early(void)
- {
- register_firmware_ops(&platformX_firmware_ops);
- }
-
-Example of using a firmware operation:
-
- /* some platform code, e.g. SMP initialization */
-
- __raw_writel(virt_to_phys(exynos4_secondary_startup),
- CPU1_BOOT_REG);
-
- /* Call Exynos specific smc call */
- if (call_firmware_op(cpu_boot, cpu) == -ENOSYS)
- cpu_boot_legacy(...); /* Try legacy way */
-
- gic_raise_softirq(cpumask_of(cpu), 1);
diff --git a/trunk/Documentation/arm/vlocks.txt b/trunk/Documentation/arm/vlocks.txt
deleted file mode 100644
index 415960a9bab0..000000000000
--- a/trunk/Documentation/arm/vlocks.txt
+++ /dev/null
@@ -1,211 +0,0 @@
-vlocks for Bare-Metal Mutual Exclusion
-======================================
-
-Voting Locks, or "vlocks" provide a simple low-level mutual exclusion
-mechanism, with reasonable but minimal requirements on the memory
-system.
-
-These are intended to be used to coordinate critical activity among CPUs
-which are otherwise non-coherent, in situations where the hardware
-provides no other mechanism to support this and ordinary spinlocks
-cannot be used.
-
-
-vlocks make use of the atomicity provided by the memory system for
-writes to a single memory location. To arbitrate, every CPU "votes for
-itself", by storing a unique number to a common memory location. The
-final value seen in that memory location when all the votes have been
-cast identifies the winner.
-
-In order to make sure that the election produces an unambiguous result
-in finite time, a CPU will only enter the election in the first place if
-no winner has been chosen and the election does not appear to have
-started yet.
-
-
-Algorithm
----------
-
-The easiest way to explain the vlocks algorithm is with some pseudo-code:
-
-
- int currently_voting[NR_CPUS] = { 0, };
- int last_vote = -1; /* no votes yet */
-
- bool vlock_trylock(int this_cpu)
- {
- /* signal our desire to vote */
- currently_voting[this_cpu] = 1;
- if (last_vote != -1) {
- /* someone already volunteered himself */
- currently_voting[this_cpu] = 0;
- return false; /* not ourself */
- }
-
- /* let's suggest ourself */
- last_vote = this_cpu;
- currently_voting[this_cpu] = 0;
-
- /* then wait until everyone else is done voting */
- for_each_cpu(i) {
- while (currently_voting[i] != 0)
- /* wait */;
- }
-
- /* result */
- if (last_vote == this_cpu)
- return true; /* we won */
- return false;
- }
-
- bool vlock_unlock(void)
- {
- last_vote = -1;
- }
-
-
-The currently_voting[] array provides a way for the CPUs to determine
-whether an election is in progress, and plays a role analogous to the
-"entering" array in Lamport's bakery algorithm [1].
-
-However, once the election has started, the underlying memory system
-atomicity is used to pick the winner. This avoids the need for a static
-priority rule to act as a tie-breaker, or any counters which could
-overflow.
-
-As long as the last_vote variable is globally visible to all CPUs, it
-will contain only one value that won't change once every CPU has cleared
-its currently_voting flag.
-
-
-Features and limitations
-------------------------
-
- * vlocks are not intended to be fair. In the contended case, it is the
- _last_ CPU which attempts to get the lock which will be most likely
- to win.
-
- vlocks are therefore best suited to situations where it is necessary
- to pick a unique winner, but it does not matter which CPU actually
- wins.
-
- * Like other similar mechanisms, vlocks will not scale well to a large
- number of CPUs.
-
- vlocks can be cascaded in a voting hierarchy to permit better scaling
- if necessary, as in the following hypothetical example for 4096 CPUs:
-
- /* first level: local election */
- my_town = towns[(this_cpu >> 4) & 0xf];
- I_won = vlock_trylock(my_town, this_cpu & 0xf);
- if (I_won) {
- /* we won the town election, let's go for the state */
- my_state = states[(this_cpu >> 8) & 0xf];
- I_won = vlock_lock(my_state, this_cpu & 0xf));
- if (I_won) {
- /* and so on */
- I_won = vlock_lock(the_whole_country, this_cpu & 0xf];
- if (I_won) {
- /* ... */
- }
- vlock_unlock(the_whole_country);
- }
- vlock_unlock(my_state);
- }
- vlock_unlock(my_town);
-
-
-ARM implementation
-------------------
-
-The current ARM implementation [2] contains some optimisations beyond
-the basic algorithm:
-
- * By packing the members of the currently_voting array close together,
- we can read the whole array in one transaction (providing the number
- of CPUs potentially contending the lock is small enough). This
- reduces the number of round-trips required to external memory.
-
- In the ARM implementation, this means that we can use a single load
- and comparison:
-
- LDR Rt, [Rn]
- CMP Rt, #0
-
- ...in place of code equivalent to:
-
- LDRB Rt, [Rn]
- CMP Rt, #0
- LDRBEQ Rt, [Rn, #1]
- CMPEQ Rt, #0
- LDRBEQ Rt, [Rn, #2]
- CMPEQ Rt, #0
- LDRBEQ Rt, [Rn, #3]
- CMPEQ Rt, #0
-
- This cuts down on the fast-path latency, as well as potentially
- reducing bus contention in contended cases.
-
- The optimisation relies on the fact that the ARM memory system
- guarantees coherency between overlapping memory accesses of
- different sizes, similarly to many other architectures. Note that
- we do not care which element of currently_voting appears in which
- bits of Rt, so there is no need to worry about endianness in this
- optimisation.
-
- If there are too many CPUs to read the currently_voting array in
- one transaction then multiple transations are still required. The
- implementation uses a simple loop of word-sized loads for this
- case. The number of transactions is still fewer than would be
- required if bytes were loaded individually.
-
-
- In principle, we could aggregate further by using LDRD or LDM, but
- to keep the code simple this was not attempted in the initial
- implementation.
-
-
- * vlocks are currently only used to coordinate between CPUs which are
- unable to enable their caches yet. This means that the
- implementation removes many of the barriers which would be required
- when executing the algorithm in cached memory.
-
- packing of the currently_voting array does not work with cached
- memory unless all CPUs contending the lock are cache-coherent, due
- to cache writebacks from one CPU clobbering values written by other
- CPUs. (Though if all the CPUs are cache-coherent, you should be
- probably be using proper spinlocks instead anyway).
-
-
- * The "no votes yet" value used for the last_vote variable is 0 (not
- -1 as in the pseudocode). This allows statically-allocated vlocks
- to be implicitly initialised to an unlocked state simply by putting
- them in .bss.
-
- An offset is added to each CPU's ID for the purpose of setting this
- variable, so that no CPU uses the value 0 for its ID.
-
-
-Colophon
---------
-
-Originally created and documented by Dave Martin for Linaro Limited, for
-use in ARM-based big.LITTLE platforms, with review and input gratefully
-received from Nicolas Pitre and Achin Gupta. Thanks to Nicolas for
-grabbing most of this text out of the relevant mail thread and writing
-up the pseudocode.
-
-Copyright (C) 2012-2013 Linaro Limited
-Distributed under the terms of Version 2 of the GNU General Public
-License, as defined in linux/COPYING.
-
-
-References
-----------
-
-[1] Lamport, L. "A New Solution of Dijkstra's Concurrent Programming
- Problem", Communications of the ACM 17, 8 (August 1974), 453-455.
-
- http://en.wikipedia.org/wiki/Lamport%27s_bakery_algorithm
-
-[2] linux/arch/arm/common/vlock.S, www.kernel.org.
diff --git a/trunk/Documentation/devicetree/bindings/arm/samsung-boards.txt b/trunk/Documentation/devicetree/bindings/arm/samsung-boards.txt
index 2168ed31e1b0..0bf68be56fd1 100644
--- a/trunk/Documentation/devicetree/bindings/arm/samsung-boards.txt
+++ b/trunk/Documentation/devicetree/bindings/arm/samsung-boards.txt
@@ -6,13 +6,3 @@ Required root node properties:
- compatible = should be one or more of the following.
(a) "samsung,smdkv310" - for Samsung's SMDKV310 eval board.
(b) "samsung,exynos4210" - for boards based on Exynos4210 SoC.
-
-Optional:
- - firmware node, specifying presence and type of secure firmware:
- - compatible: only "samsung,secure-firmware" is currently supported
- - reg: address of non-secure SYSRAM used for communication with firmware
-
- firmware@0203F000 {
- compatible = "samsung,secure-firmware";
- reg = <0x0203F000 0x1000>;
- };
diff --git a/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt b/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt
index 4b87ea1194e3..5ddb2e9efaaa 100644
--- a/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt
+++ b/trunk/Documentation/devicetree/bindings/bus/ti-gpmc.txt
@@ -35,83 +35,36 @@ Required properties:
Timing properties for child nodes. All are optional and default to 0.
- - gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
-
- Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
- - gpmc,cs-on-ns: Assertion time
- - gpmc,cs-rd-off-ns: Read deassertion time
- - gpmc,cs-wr-off-ns: Write deassertion time
-
- ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
- - gpmc,adv-on-ns: Assertion time
- - gpmc,adv-rd-off-ns: Read deassertion time
- - gpmc,adv-wr-off-ns: Write deassertion time
-
- WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
- - gpmc,we-on-ns Assertion time
- - gpmc,we-off-ns: Deassertion time
-
- OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
- - gpmc,oe-on-ns: Assertion time
- - gpmc,oe-off-ns: Deassertion time
-
- Access time and cycle time timings (in nanoseconds) corresponding to
- GPMC_CONFIG5:
- - gpmc,page-burst-access-ns: Multiple access word delay
- - gpmc,access-ns: Start-cycle to first data valid delay
- - gpmc,rd-cycle-ns: Total read cycle time
- - gpmc,wr-cycle-ns: Total write cycle time
- - gpmc,bus-turnaround-ns: Turn-around time between successive accesses
- - gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
- - gpmc,clk-activation-ns: GPMC clock activation time
- - gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
- data
-
-Boolean timing parameters. If property is present parameter enabled and
-disabled if omitted:
- - gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
- - gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
- - gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
- accesses to a different CS
- - gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
- accesses to the same CS
- - gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
- - gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
- - gpmc,time-para-granularity: Multiply all access times by 2
+ - gpmc,sync-clk: Minimum clock period for synchronous mode, in picoseconds
+
+ Chip-select signal timings corresponding to GPMC_CONFIG2:
+ - gpmc,cs-on: Assertion time
+ - gpmc,cs-rd-off: Read deassertion time
+ - gpmc,cs-wr-off: Write deassertion time
+
+ ADV signal timings corresponding to GPMC_CONFIG3:
+ - gpmc,adv-on: Assertion time
+ - gpmc,adv-rd-off: Read deassertion time
+ - gpmc,adv-wr-off: Write deassertion time
+
+ WE signals timings corresponding to GPMC_CONFIG4:
+ - gpmc,we-on: Assertion time
+ - gpmc,we-off: Deassertion time
+
+ OE signals timings corresponding to GPMC_CONFIG4:
+ - gpmc,oe-on: Assertion time
+ - gpmc,oe-off: Deassertion time
+
+ Access time and cycle time timings corresponding to GPMC_CONFIG5:
+ - gpmc,page-burst-access: Multiple access word delay
+ - gpmc,access: Start-cycle to first data valid delay
+ - gpmc,rd-cycle: Total read cycle time
+ - gpmc,wr-cycle: Total write cycle time
The following are only applicable to OMAP3+ and AM335x:
- - gpmc,wr-access-ns: In synchronous write mode, for single or
- burst accesses, defines the number of
- GPMC_FCLK cycles from start access time
- to the GPMC_CLK rising edge used by the
- memory device for the first data capture.
- - gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
- the time when the first data is driven on
- the address-data bus.
-
-GPMC chip-select settings properties for child nodes. All are optional.
-
-- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
-- gpmc,burst-wrap Enables wrap bursting
-- gpmc,burst-read Enables read page/burst mode
-- gpmc,burst-write Enables write page/burst mode
-- gpmc,device-nand Device is NAND
-- gpmc,device-width Total width of device(s) connected to a GPMC
- chip-select in bytes. The GPMC supports 8-bit
- and 16-bit devices and so this property must be
- 1 or 2.
-- gpmc,mux-add-data Address and data multiplexing configuration.
- Valid values are 1 for address-address-data
- multiplexing mode and 2 for address-data
- multiplexing mode.
-- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
- is this is not set.
-- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
- is this is not set.
-- gpmc,wait-pin Wait-pin used by client. Must be less than
- "gpmc,num-waitpins".
-- gpmc,wait-on-read Enables wait monitoring on reads.
-- gpmc,wait-on-write Enables wait monitoring on writes.
+ - gpmc,wr-access
+ - gpmc,wr-data-mux-bus
+
Example for an AM33xx board:
diff --git a/trunk/Documentation/devicetree/bindings/clock/exynos4-clock.txt b/trunk/Documentation/devicetree/bindings/clock/exynos4-clock.txt
deleted file mode 100644
index ea5e26f16aec..000000000000
--- a/trunk/Documentation/devicetree/bindings/clock/exynos4-clock.txt
+++ /dev/null
@@ -1,288 +0,0 @@
-* Samsung Exynos4 Clock Controller
-
-The Exynos4 clock controller generates and supplies clock to various controllers
-within the Exynos4 SoC. The clock binding described here is applicable to all
-SoC's in the Exynos4 family.
-
-Required Properties:
-
-- comptible: should be one of the following.
- - "samsung,exynos4210-clock" - controller compatible with Exynos4210 SoC.
- - "samsung,exynos4412-clock" - controller compatible with Exynos4412 SoC.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-The following is the list of clocks generated by the controller. Each clock is
-assigned an identifier and client nodes use this identifier to specify the
-clock which they consume. Some of the clocks are available only on a particular
-Exynos4 SoC and this is specified where applicable.
-
-
- [Core Clocks]
-
- Clock ID SoC (if specific)
- -----------------------------------------------
-
- xxti 1
- xusbxti 2
- fin_pll 3
- fout_apll 4
- fout_mpll 5
- fout_epll 6
- fout_vpll 7
- sclk_apll 8
- sclk_mpll 9
- sclk_epll 10
- sclk_vpll 11
- arm_clk 12
- aclk200 13
- aclk100 14
- aclk160 15
- aclk133 16
- mout_mpll_user_t 17 Exynos4x12
- mout_mpll_user_c 18 Exynos4x12
- mout_core 19
- mout_apll 20
-
-
- [Clock Gate for Special Clocks]
-
- Clock ID SoC (if specific)
- -----------------------------------------------
-
- sclk_fimc0 128
- sclk_fimc1 129
- sclk_fimc2 130
- sclk_fimc3 131
- sclk_cam0 132
- sclk_cam1 133
- sclk_csis0 134
- sclk_csis1 135
- sclk_hdmi 136
- sclk_mixer 137
- sclk_dac 138
- sclk_pixel 139
- sclk_fimd0 140
- sclk_mdnie0 141 Exynos4412
- sclk_mdnie_pwm0 12 142 Exynos4412
- sclk_mipi0 143
- sclk_audio0 144
- sclk_mmc0 145
- sclk_mmc1 146
- sclk_mmc2 147
- sclk_mmc3 148
- sclk_mmc4 149
- sclk_sata 150 Exynos4210
- sclk_uart0 151
- sclk_uart1 152
- sclk_uart2 153
- sclk_uart3 154
- sclk_uart4 155
- sclk_audio1 156
- sclk_audio2 157
- sclk_spdif 158
- sclk_spi0 159
- sclk_spi1 160
- sclk_spi2 161
- sclk_slimbus 162
- sclk_fimd1 163 Exynos4210
- sclk_mipi1 164 Exynos4210
- sclk_pcm1 165
- sclk_pcm2 166
- sclk_i2s1 167
- sclk_i2s2 168
- sclk_mipihsi 169 Exynos4412
- sclk_mfc 170
- sclk_pcm0 171
- sclk_g3d 172
- sclk_pwm_isp 173 Exynos4x12
- sclk_spi0_isp 174 Exynos4x12
- sclk_spi1_isp 175 Exynos4x12
- sclk_uart_isp 176 Exynos4x12
-
- [Peripheral Clock Gates]
-
- Clock ID SoC (if specific)
- -----------------------------------------------
-
- fimc0 256
- fimc1 257
- fimc2 258
- fimc3 259
- csis0 260
- csis1 261
- jpeg 262
- smmu_fimc0 263
- smmu_fimc1 264
- smmu_fimc2 265
- smmu_fimc3 266
- smmu_jpeg 267
- vp 268
- mixer 269
- tvenc 270 Exynos4210
- hdmi 271
- smmu_tv 272
- mfc 273
- smmu_mfcl 274
- smmu_mfcr 275
- g3d 276
- g2d 277 Exynos4210
- rotator 278 Exynos4210
- mdma 279 Exynos4210
- smmu_g2d 280 Exynos4210
- smmu_rotator 281 Exynos4210
- smmu_mdma 282 Exynos4210
- fimd0 283
- mie0 284
- mdnie0 285 Exynos4412
- dsim0 286
- smmu_fimd0 287
- fimd1 288 Exynos4210
- mie1 289 Exynos4210
- dsim1 290 Exynos4210
- smmu_fimd1 291 Exynos4210
- pdma0 292
- pdma1 293
- pcie_phy 294
- sata_phy 295 Exynos4210
- tsi 296
- sdmmc0 297
- sdmmc1 298
- sdmmc2 299
- sdmmc3 300
- sdmmc4 301
- sata 302 Exynos4210
- sromc 303
- usb_host 304
- usb_device 305
- pcie 306
- onenand 307
- nfcon 308
- smmu_pcie 309
- gps 310
- smmu_gps 311
- uart0 312
- uart1 313
- uart2 314
- uart3 315
- uart4 316
- i2c0 317
- i2c1 318
- i2c2 319
- i2c3 320
- i2c4 321
- i2c5 322
- i2c6 323
- i2c7 324
- i2c_hdmi 325
- tsadc 326
- spi0 327
- spi1 328
- spi2 329
- i2s1 330
- i2s2 331
- pcm0 332
- i2s0 333
- pcm1 334
- pcm2 335
- pwm 336
- slimbus 337
- spdif 338
- ac97 339
- modemif 340
- chipid 341
- sysreg 342
- hdmi_cec 343
- mct 344
- wdt 345
- rtc 346
- keyif 347
- audss 348
- mipi_hsi 349 Exynos4210
- mdma2 350 Exynos4210
- pixelasyncm0 351
- pixelasyncm1 352
- fimc_lite0 353 Exynos4x12
- fimc_lite1 354 Exynos4x12
- ppmuispx 355 Exynos4x12
- ppmuispmx 356 Exynos4x12
- fimc_isp 357 Exynos4x12
- fimc_drc 358 Exynos4x12
- fimc_fd 359 Exynos4x12
- mcuisp 360 Exynos4x12
- gicisp 361 Exynos4x12
- smmu_isp 362 Exynos4x12
- smmu_drc 363 Exynos4x12
- smmu_fd 364 Exynos4x12
- smmu_lite0 365 Exynos4x12
- smmu_lite1 366 Exynos4x12
- mcuctl_isp 367 Exynos4x12
- mpwm_isp 368 Exynos4x12
- i2c0_isp 369 Exynos4x12
- i2c1_isp 370 Exynos4x12
- mtcadc_isp 371 Exynos4x12
- pwm_isp 372 Exynos4x12
- wdt_isp 373 Exynos4x12
- uart_isp 374 Exynos4x12
- asyncaxim 375 Exynos4x12
- smmu_ispcx 376 Exynos4x12
- spi0_isp 377 Exynos4x12
- spi1_isp 378 Exynos4x12
- pwm_isp_sclk 379 Exynos4x12
- spi0_isp_sclk 380 Exynos4x12
- spi1_isp_sclk 381 Exynos4x12
- uart_isp_sclk 382 Exynos4x12
-
- [Mux Clocks]
-
- Clock ID SoC (if specific)
- -----------------------------------------------
-
- mout_fimc0 384
- mout_fimc1 385
- mout_fimc2 386
- mout_fimc3 387
- mout_cam0 388
- mout_cam1 389
- mout_csis0 390
- mout_csis1 391
- mout_g3d0 392
- mout_g3d1 393
- mout_g3d 394
- aclk400_mcuisp 395 Exynos4x12
-
- [Div Clocks]
-
- Clock ID SoC (if specific)
- -----------------------------------------------
-
- div_isp0 450 Exynos4x12
- div_isp1 451 Exynos4x12
- div_mcuisp0 452 Exynos4x12
- div_mcuisp1 453 Exynos4x12
- div_aclk200 454 Exynos4x12
- div_aclk400_mcuisp 455 Exynos4x12
-
-
-Example 1: An example of a clock controller node is listed below.
-
- clock: clock-controller@0x10030000 {
- compatible = "samsung,exynos4210-clock";
- reg = <0x10030000 0x20000>;
- #clock-cells = <1>;
- };
-
-Example 2: UART controller node that consumes the clock generated by the clock
- controller. Refer to the standard clock bindings for information
- about 'clocks' and 'clock-names' property.
-
- serial@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <0 54 0>;
- clocks = <&clock 314>, <&clock 153>;
- clock-names = "uart", "clk_uart_baud0";
- };
diff --git a/trunk/Documentation/devicetree/bindings/clock/exynos5250-clock.txt b/trunk/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
deleted file mode 100644
index 781a6276adf7..000000000000
--- a/trunk/Documentation/devicetree/bindings/clock/exynos5250-clock.txt
+++ /dev/null
@@ -1,177 +0,0 @@
-* Samsung Exynos5250 Clock Controller
-
-The Exynos5250 clock controller generates and supplies clock to various
-controllers within the Exynos5250 SoC.
-
-Required Properties:
-
-- comptible: should be one of the following.
- - "samsung,exynos5250-clock" - controller compatible with Exynos5250 SoC.
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-The following is the list of clocks generated by the controller. Each clock is
-assigned an identifier and client nodes use this identifier to specify the
-clock which they consume.
-
-
- [Core Clocks]
-
- Clock ID
- ----------------------------
-
- fin_pll 1
-
- [Clock Gate for Special Clocks]
-
- Clock ID
- ----------------------------
-
- sclk_cam_bayer 128
- sclk_cam0 129
- sclk_cam1 130
- sclk_gscl_wa 131
- sclk_gscl_wb 132
- sclk_fimd1 133
- sclk_mipi1 134
- sclk_dp 135
- sclk_hdmi 136
- sclk_pixel 137
- sclk_audio0 138
- sclk_mmc0 139
- sclk_mmc1 140
- sclk_mmc2 141
- sclk_mmc3 142
- sclk_sata 143
- sclk_usb3 144
- sclk_jpeg 145
- sclk_uart0 146
- sclk_uart1 147
- sclk_uart2 148
- sclk_uart3 149
- sclk_pwm 150
- sclk_audio1 151
- sclk_audio2 152
- sclk_spdif 153
- sclk_spi0 154
- sclk_spi1 155
- sclk_spi2 156
-
-
- [Peripheral Clock Gates]
-
- Clock ID
- ----------------------------
-
- gscl0 256
- gscl1 257
- gscl2 258
- gscl3 259
- gscl_wa 260
- gscl_wb 261
- smmu_gscl0 262
- smmu_gscl1 263
- smmu_gscl2 264
- smmu_gscl3 265
- mfc 266
- smmu_mfcl 267
- smmu_mfcr 268
- rotator 269
- jpeg 270
- mdma1 271
- smmu_rotator 272
- smmu_jpeg 273
- smmu_mdma1 274
- pdma0 275
- pdma1 276
- sata 277
- usbotg 278
- mipi_hsi 279
- sdmmc0 280
- sdmmc1 281
- sdmmc2 282
- sdmmc3 283
- sromc 284
- usb2 285
- usb3 286
- sata_phyctrl 287
- sata_phyi2c 288
- uart0 289
- uart1 290
- uart2 291
- uart3 292
- uart4 293
- i2c0 294
- i2c1 295
- i2c2 296
- i2c3 297
- i2c4 298
- i2c5 299
- i2c6 300
- i2c7 301
- i2c_hdmi 302
- adc 303
- spi0 304
- spi1 305
- spi2 306
- i2s1 307
- i2s2 308
- pcm1 309
- pcm2 310
- pwm 311
- spdif 312
- ac97 313
- hsi2c0 314
- hsi2c1 315
- hs12c2 316
- hs12c3 317
- chipid 318
- sysreg 319
- pmu 320
- cmu_top 321
- cmu_core 322
- cmu_mem 323
- tzpc0 324
- tzpc1 325
- tzpc2 326
- tzpc3 327
- tzpc4 328
- tzpc5 329
- tzpc6 330
- tzpc7 331
- tzpc8 332
- tzpc9 333
- hdmi_cec 334
- mct 335
- wdt 336
- rtc 337
- tmu 338
- fimd1 339
- mie1 340
- dsim0 341
- dp 342
- mixer 343
- hdmi 345
-
-Example 1: An example of a clock controller node is listed below.
-
- clock: clock-controller@0x10010000 {
- compatible = "samsung,exynos5250-clock";
- reg = <0x10010000 0x30000>;
- #clock-cells = <1>;
- };
-
-Example 2: UART controller node that consumes the clock generated by the clock
- controller. Refer to the standard clock bindings for information
- about 'clocks' and 'clock-names' property.
-
- serial@13820000 {
- compatible = "samsung,exynos4210-uart";
- reg = <0x13820000 0x100>;
- interrupts = <0 54 0>;
- clocks = <&clock 314>, <&clock 153>;
- clock-names = "uart", "clk_uart_baud0";
- };
diff --git a/trunk/Documentation/devicetree/bindings/clock/exynos5440-clock.txt b/trunk/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
deleted file mode 100644
index 4499e9966bc9..000000000000
--- a/trunk/Documentation/devicetree/bindings/clock/exynos5440-clock.txt
+++ /dev/null
@@ -1,61 +0,0 @@
-* Samsung Exynos5440 Clock Controller
-
-The Exynos5440 clock controller generates and supplies clock to various
-controllers within the Exynos5440 SoC.
-
-Required Properties:
-
-- comptible: should be "samsung,exynos5440-clock".
-
-- reg: physical base address of the controller and length of memory mapped
- region.
-
-- #clock-cells: should be 1.
-
-The following is the list of clocks generated by the controller. Each clock is
-assigned an identifier and client nodes use this identifier to specify the
-clock which they consume.
-
-
- [Core Clocks]
-
- Clock ID
- ----------------------------
-
- xtal 1
- arm_clk 2
-
- [Peripheral Clock Gates]
-
- Clock ID
- ----------------------------
-
- spi_baud 16
- pb0_250 17
- pr0_250 18
- pr1_250 19
- b_250 20
- b_125 21
- b_200 22
- sata 23
- usb 24
- gmac0 25
- cs250 26
- pb0_250_o 27
- pr0_250_o 28
- pr1_250_o 29
- b_250_o 30
- b_125_o 31
- b_200_o 32
- sata_o 33
- usb_o 34
- gmac0_o 35
- cs250_o 36
-
-Example: An example of a clock controller node is listed below.
-
- clock: clock-controller@0x10010000 {
- compatible = "samsung,exynos5440-clock";
- reg = <0x160000 0x10000>;
- #clock-cells = <1>;
- };
diff --git a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
deleted file mode 100644
index d6cb083b90a2..000000000000
--- a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra114-car.txt
+++ /dev/null
@@ -1,303 +0,0 @@
-NVIDIA Tegra114 Clock And Reset Controller
-
-This binding uses the common clock binding:
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-
-The CAR (Clock And Reset) Controller on Tegra is the HW module responsible
-for muxing and gating Tegra's clocks, and setting their rates.
-
-Required properties :
-- compatible : Should be "nvidia,tegra114-car"
-- reg : Should contain CAR registers location and length
-- clocks : Should contain phandle and clock specifiers for two clocks:
- the 32 KHz "32k_in", and the board-specific oscillator "osc".
-- #clock-cells : Should be 1.
- In clock consumers, this cell represents the clock ID exposed by the CAR.
-
- The first 160 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
- registers. These IDs often match those in the CAR's RST_DEVICES registers,
- but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
- this case, those clocks are assigned IDs above 160 in order to highlight
- this issue. Implementations that interpret these clock IDs as bit values
- within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
- explicitly handle these special cases.
-
- The balance of the clocks controlled by the CAR are assigned IDs of 160 and
- above.
-
- 0 unassigned
- 1 unassigned
- 2 unassigned
- 3 unassigned
- 4 rtc
- 5 timer
- 6 uarta
- 7 unassigned (register bit affects uartb and vfir)
- 8 unassigned
- 9 sdmmc2
- 10 unassigned (register bit affects spdif_in and spdif_out)
- 11 i2s1
- 12 i2c1
- 13 ndflash
- 14 sdmmc1
- 15 sdmmc4
- 16 unassigned
- 17 pwm
- 18 i2s2
- 19 epp
- 20 unassigned (register bit affects vi and vi_sensor)
- 21 2d
- 22 usbd
- 23 isp
- 24 3d
- 25 unassigned
- 26 disp2
- 27 disp1
- 28 host1x
- 29 vcp
- 30 i2s0
- 31 unassigned
-
- 32 unassigned
- 33 unassigned
- 34 apbdma
- 35 unassigned
- 36 kbc
- 37 unassigned
- 38 unassigned
- 39 unassigned (register bit affects fuse and fuse_burn)
- 40 kfuse
- 41 sbc1
- 42 nor
- 43 unassigned
- 44 sbc2
- 45 unassigned
- 46 sbc3
- 47 i2c5
- 48 dsia
- 49 unassigned
- 50 mipi
- 51 hdmi
- 52 csi
- 53 unassigned
- 54 i2c2
- 55 uartc
- 56 mipi-cal
- 57 emc
- 58 usb2
- 59 usb3
- 60 msenc
- 61 vde
- 62 bsea
- 63 bsev
-
- 64 unassigned
- 65 uartd
- 66 unassigned
- 67 i2c3
- 68 sbc4
- 69 sdmmc3
- 70 unassigned
- 71 owr
- 72 afi
- 73 csite
- 74 unassigned
- 75 unassigned
- 76 la
- 77 trace
- 78 soc_therm
- 79 dtv
- 80 ndspeed
- 81 i2cslow
- 82 dsib
- 83 tsec
- 84 unassigned
- 85 unassigned
- 86 unassigned
- 87 unassigned
- 88 unassigned
- 89 xusb_host
- 90 unassigned
- 91 msenc
- 92 csus
- 93 unassigned
- 94 unassigned
- 95 unassigned (bit affects xusb_dev and xusb_dev_src)
-
- 96 unassigned
- 97 unassigned
- 98 unassigned
- 99 mselect
- 100 tsensor
- 101 i2s3
- 102 i2s4
- 103 i2c4
- 104 sbc5
- 105 sbc6
- 106 d_audio
- 107 apbif
- 108 dam0
- 109 dam1
- 110 dam2
- 111 hda2codec_2x
- 112 unassigned
- 113 audio0_2x
- 114 audio1_2x
- 115 audio2_2x
- 116 audio3_2x
- 117 audio4_2x
- 118 spdif_2x
- 119 actmon
- 120 extern1
- 121 extern2
- 122 extern3
- 123 unassigned
- 124 unassigned
- 125 hda
- 126 unassigned
- 127 se
-
- 128 hda2hdmi
- 129 unassigned
- 130 unassigned
- 131 unassigned
- 132 unassigned
- 133 unassigned
- 134 unassigned
- 135 unassigned
- 136 unassigned
- 137 unassigned
- 138 unassigned
- 139 unassigned
- 140 unassigned
- 141 unassigned
- 142 unassigned
- 143 unassigned (bit affects xusb_falcon_src, xusb_fs_src,
- xusb_host_src and xusb_ss_src)
- 144 cilab
- 145 cilcd
- 146 cile
- 147 dsialp
- 148 dsiblp
- 149 unassigned
- 150 dds
- 151 unassigned
- 152 dp2
- 153 amx
- 154 adx
- 155 unassigned (bit affects dfll_ref and dfll_soc)
- 156 xusb_ss
-
- 192 uartb
- 193 vfir
- 194 spdif_in
- 195 spdif_out
- 196 vi
- 197 vi_sensor
- 198 fuse
- 199 fuse_burn
- 200 clk_32k
- 201 clk_m
- 202 clk_m_div2
- 203 clk_m_div4
- 204 pll_ref
- 205 pll_c
- 206 pll_c_out1
- 207 pll_c2
- 208 pll_c3
- 209 pll_m
- 210 pll_m_out1
- 211 pll_p
- 212 pll_p_out1
- 213 pll_p_out2
- 214 pll_p_out3
- 215 pll_p_out4
- 216 pll_a
- 217 pll_a_out0
- 218 pll_d
- 219 pll_d_out0
- 220 pll_d2
- 221 pll_d2_out0
- 222 pll_u
- 223 pll_u_480M
- 224 pll_u_60M
- 225 pll_u_48M
- 226 pll_u_12M
- 227 pll_x
- 228 pll_x_out0
- 229 pll_re_vco
- 230 pll_re_out
- 231 pll_e_out0
- 232 spdif_in_sync
- 233 i2s0_sync
- 234 i2s1_sync
- 235 i2s2_sync
- 236 i2s3_sync
- 237 i2s4_sync
- 238 vimclk_sync
- 239 audio0
- 240 audio1
- 241 audio2
- 242 audio3
- 243 audio4
- 244 spdif
- 245 clk_out_1
- 246 clk_out_2
- 247 clk_out_3
- 248 blink
- 252 xusb_host_src
- 253 xusb_falcon_src
- 254 xusb_fs_src
- 255 xusb_ss_src
- 256 xusb_dev_src
- 257 xusb_dev
- 258 xusb_hs_src
- 259 sclk
- 260 hclk
- 261 pclk
- 262 cclk_g
- 263 cclk_lp
- 264 dfll_ref
- 265 dfll_soc
-
-Example SoC include file:
-
-/ {
- tegra_car: clock {
- compatible = "nvidia,tegra114-car";
- reg = <0x60006000 0x1000>;
- #clock-cells = <1>;
- };
-
- usb@c5004000 {
- clocks = <&tegra_car 58>; /* usb2 */
- };
-};
-
-Example board file:
-
-/ {
- clocks {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- osc: clock@0 {
- compatible = "fixed-clock";
- reg = <0>;
- #clock-cells = <0>;
- clock-frequency = <12000000>;
- };
-
- clk_32k: clock@1 {
- compatible = "fixed-clock";
- reg = <1>;
- #clock-cells = <0>;
- clock-frequency = <32768>;
- };
- };
-
- &tegra_car {
- clocks = <&clk_32k> <&osc>;
- };
-};
diff --git a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
index e885680f6b45..0921fac73528 100644
--- a/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
+++ b/trunk/Documentation/devicetree/bindings/clock/nvidia,tegra20-car.txt
@@ -120,8 +120,8 @@ Required properties :
90 clk_d
91 unassigned
92 sus
- 93 cdev2
- 94 cdev1
+ 93 cdev1
+ 94 cdev2
95 unassigned
96 uart2
diff --git a/trunk/Documentation/devicetree/bindings/drm/exynos/g2d.txt b/trunk/Documentation/devicetree/bindings/drm/exynos/g2d.txt
new file mode 100644
index 000000000000..1eb124d35a99
--- /dev/null
+++ b/trunk/Documentation/devicetree/bindings/drm/exynos/g2d.txt
@@ -0,0 +1,22 @@
+Samsung 2D Graphic Accelerator using DRM frame work
+
+Samsung FIMG2D is a graphics 2D accelerator which supports Bit Block Transfer.
+We set the drawing-context registers for configuring rendering parameters and
+then start rendering.
+This driver is for SOCs which contain G2D IPs with version 4.1.
+
+Required properties:
+ -compatible:
+ should be "samsung,exynos-g2d-41".
+ -reg:
+ physical base address of the controller and length
+ of memory mapped region.
+ -interrupts:
+ interrupt combiner values.
+
+Example:
+ g2d {
+ compatible = "samsung,exynos-g2d-41";
+ reg = <0x10850000 0x1000>;
+ interrupts = <0 91 0>;
+ };
diff --git a/trunk/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt b/trunk/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
new file mode 100644
index 000000000000..f4dc5233167e
--- /dev/null
+++ b/trunk/Documentation/devicetree/bindings/gpio/gpio-vt8500.txt
@@ -0,0 +1,24 @@
+VIA/Wondermedia VT8500 GPIO Controller
+-----------------------------------------------------
+
+Required properties:
+- compatible : "via,vt8500-gpio", "wm,wm8505-gpio"
+ or "wm,wm8650-gpio" depending on your SoC
+- reg : Should contain 1 register range (address and length)
+- #gpio-cells : should be <3>.
+ 1) bank
+ 2) pin number
+ 3) flags - should be 0
+
+Example:
+
+ gpio: gpio-controller@d8110000 {
+ compatible = "via,vt8500-gpio";
+ gpio-controller;
+ reg = <0xd8110000 0x10000>;
+ #gpio-cells = <3>;
+ };
+
+ vibrate {
+ gpios = <&gpio 0 1 0>; /* Bank 0, Pin 1, No flags */
+ };
diff --git a/trunk/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt b/trunk/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
index 9b3f1d4a88d6..e13787498bcf 100644
--- a/trunk/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
+++ b/trunk/Documentation/devicetree/bindings/gpio/mrvl-gpio.txt
@@ -1,10 +1,7 @@
* Marvell PXA GPIO controller
Required properties:
-- compatible : Should be "intel,pxa25x-gpio", "intel,pxa26x-gpio",
- "intel,pxa27x-gpio", "intel,pxa3xx-gpio",
- "marvell,pxa93x-gpio", "marvell,mmp-gpio" or
- "marvell,mmp2-gpio".
+- compatible : Should be "mrvl,pxa-gpio" or "mrvl,mmp-gpio"
- reg : Address and length of the register set for the device
- interrupts : Should be the port interrupt shared by all gpio pins.
There're three gpio interrupts in arch-pxa, and they're gpio0,
@@ -21,7 +18,7 @@ Required properties:
Example:
gpio: gpio@d4019000 {
- compatible = "marvell,mmp-gpio";
+ compatible = "mrvl,mmp-gpio";
reg = <0xd4019000 0x1000>;
interrupts = <49>;
interrupt-name = "gpio_mux";
diff --git a/trunk/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt b/trunk/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
deleted file mode 100644
index c54c5a9a2a90..000000000000
--- a/trunk/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt
+++ /dev/null
@@ -1,53 +0,0 @@
-Samsung S3C24XX Interrupt Controllers
-
-The S3C24XX SoCs contain a custom set of interrupt controllers providing a
-varying number of interrupt sources. The set consists of a main- and sub-
-controller and on newer SoCs even a second main controller.
-
-Required properties:
-- compatible: Compatible property value should be "samsung,s3c2410-irq"
- for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later.
-
-- reg: Physical base address of the controller and length of memory mapped
- region.
-
-- interrupt-controller : Identifies the node as an interrupt controller
-
-- #interrupt-cells : Specifies the number of cells needed to encode an
- interrupt source. The value shall be 4 and interrupt descriptor shall
- have the following format:
-
-
- ctrl_num contains the controller to use:
- - 0 ... main controller
- - 1 ... sub controller
- - 2 ... second main controller on s3c2416 and s3c2450
- parent_irq contains the parent bit in the main controller and will be
- ignored in main controllers
- ctrl_irq contains the interrupt bit of the controller
- type contains the trigger type to use
-
-Example:
-
- interrupt-controller@4a000000 {
- compatible = "samsung,s3c2410-irq";
- reg = <0x4a000000 0x100>;
- interrupt-controller;
- #interrupt-cells=<4>;
- };
-
- [...]
-
- serial@50000000 {
- compatible = "samsung,s3c2410-uart";
- reg = <0x50000000 0x4000>;
- interrupt-parent = <&subintc>;
- interrupts = <1 28 0 4>, <1 28 1 4>;
- };
-
- rtc@57000000 {
- compatible = "samsung,s3c2410-rtc";
- reg = <0x57000000 0x100>;
- interrupt-parent = <&intc>;
- interrupts = <0 30 0 3>, <0 8 0 3>;
- };
diff --git a/trunk/Documentation/devicetree/bindings/media/s5p-mfc.txt b/trunk/Documentation/devicetree/bindings/media/s5p-mfc.txt
index bf0182d8da25..67ec3d4ccc7f 100644
--- a/trunk/Documentation/devicetree/bindings/media/s5p-mfc.txt
+++ b/trunk/Documentation/devicetree/bindings/media/s5p-mfc.txt
@@ -21,24 +21,3 @@ Required properties:
- samsung,mfc-l : Base address of the second memory bank used by MFC
for DMA contiguous memory allocation and its size.
-
-Optional properties:
- - samsung,power-domain : power-domain property defined with a phandle
- to respective power domain.
-
-Example:
-SoC specific DT entry:
-
-mfc: codec@13400000 {
- compatible = "samsung,mfc-v5";
- reg = <0x13400000 0x10000>;
- interrupts = <0 94 0>;
- samsung,power-domain = <&pd_mfc>;
-};
-
-Board specific DT entry:
-
-codec@13400000 {
- samsung,mfc-r = <0x43000000 0x800000>;
- samsung,mfc-l = <0x51000000 0x800000>;
-};
diff --git a/trunk/Documentation/devicetree/bindings/misc/smc.txt b/trunk/Documentation/devicetree/bindings/misc/smc.txt
deleted file mode 100644
index 02b428136177..000000000000
--- a/trunk/Documentation/devicetree/bindings/misc/smc.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Broadcom Secure Monitor Bounce buffer
------------------------------------------------------
-This binding defines the location of the bounce buffer
-used for non-secure to secure communications.
-
-Required properties:
-- compatible : "bcm,kona-smc"
-- reg : Location and size of bounce buffer
-
-Example:
- smc@0x3404c000 {
- compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
- reg = <0x3404c000 0x400>; //1 KiB in SRAM
- };
diff --git a/trunk/Documentation/devicetree/bindings/mtd/gpmc-nor.txt b/trunk/Documentation/devicetree/bindings/mtd/gpmc-nor.txt
deleted file mode 100644
index 420b3ab18890..000000000000
--- a/trunk/Documentation/devicetree/bindings/mtd/gpmc-nor.txt
+++ /dev/null
@@ -1,98 +0,0 @@
-Device tree bindings for NOR flash connect to TI GPMC
-
-NOR flash connected to the TI GPMC (found on OMAP boards) are represented as
-child nodes of the GPMC controller with a name of "nor".
-
-All timing relevant properties as well as generic GPMC child properties are
-explained in a separate documents. Please refer to
-Documentation/devicetree/bindings/bus/ti-gpmc.txt
-
-Required properties:
-- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
- 16-bit devices and so must be either 1 or 2 bytes.
-- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
-- gpmc,cs-on-ns: Chip-select assertion time
-- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
-- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
-- gpmc,oe-on-ns: Output-enable assertion time
-- gpmc,oe-off-ns: Output-enable de-assertion time
-- gpmc,we-on-ns Write-enable assertion time
-- gpmc,we-off-ns: Write-enable de-assertion time
-- gpmc,access-ns: Start cycle to first data capture (read access)
-- gpmc,rd-cycle-ns: Total read cycle time
-- gpmc,wr-cycle-ns: Total write cycle time
-- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.txt
-- reg: Chip-select, base address (relative to chip-select)
- and size of NOR flash. Note that base address will be
- typically 0 as this is the start of the chip-select.
-
-Optional properties:
-- gpmc,XXX Additional GPMC timings and settings parameters. See
- Documentation/devicetree/bindings/bus/ti-gpmc.txt
-
-Optional properties for partiton table parsing:
-- #address-cells: should be set to 1
-- #size-cells: should be set to 1
-
-Example:
-
-gpmc: gpmc@6e000000 {
- compatible = "ti,omap3430-gpmc", "simple-bus";
- ti,hwmods = "gpmc";
- reg = <0x6e000000 0x1000>;
- interrupts = <20>;
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- #address-cells = <2>;
- #size-cells = <1>;
-
- ranges = <0 0 0x10000000 0x08000000>;
-
- nor@0,0 {
- compatible = "cfi-flash";
- linux,mtd-name= "intel,pf48f6000m0y1be";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0 0 0x08000000>;
- bank-width = <2>;
-
- gpmc,mux-add-data;
- gpmc,cs-on-ns = <0>;
- gpmc,cs-rd-off-ns = <186>;
- gpmc,cs-wr-off-ns = <186>;
- gpmc,adv-on-ns = <12>;
- gpmc,adv-rd-off-ns = <48>;
- gpmc,adv-wr-off-ns = <48>;
- gpmc,oe-on-ns = <54>;
- gpmc,oe-off-ns = <168>;
- gpmc,we-on-ns = <54>;
- gpmc,we-off-ns = <168>;
- gpmc,rd-cycle-ns = <186>;
- gpmc,wr-cycle-ns = <186>;
- gpmc,access-ns = <114>;
- gpmc,page-burst-access-ns = <6>;
- gpmc,bus-turnaround-ns = <12>;
- gpmc,cycle2cycle-delay-ns = <18>;
- gpmc,wr-data-mux-bus-ns = <90>;
- gpmc,wr-access-ns = <186>;
- gpmc,cycle2cycle-samecsen;
- gpmc,cycle2cycle-diffcsen;
-
- partition@0 {
- label = "bootloader-nor";
- reg = <0 0x40000>;
- };
- partition@0x40000 {
- label = "params-nor";
- reg = <0x40000 0x40000>;
- };
- partition@0x80000 {
- label = "kernel-nor";
- reg = <0x80000 0x200000>;
- };
- partition@0x280000 {
- label = "filesystem-nor";
- reg = <0x240000 0x7d80000>;
- };
- };
-};
diff --git a/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt b/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
index b7529424ac88..deec9da224a2 100644
--- a/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
+++ b/trunk/Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
@@ -10,8 +10,6 @@ Documentation/devicetree/bindings/bus/ti-gpmc.txt
Required properties:
- reg: The CS line the peripheral is connected to
- - gpmc,device-width Width of the ONENAND device connected to the GPMC
- in bytes. Must be 1 or 2.
Optional properties:
@@ -36,7 +34,6 @@ Example for an OMAP3430 board:
onenand@0 {
reg = <0 0 0>; /* CS0, offset 0 */
- gpmc,device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/trunk/Documentation/devicetree/bindings/net/gpmc-eth.txt b/trunk/Documentation/devicetree/bindings/net/gpmc-eth.txt
deleted file mode 100644
index 24cb4e46f675..000000000000
--- a/trunk/Documentation/devicetree/bindings/net/gpmc-eth.txt
+++ /dev/null
@@ -1,97 +0,0 @@
-Device tree bindings for Ethernet chip connected to TI GPMC
-
-Besides being used to interface with external memory devices, the
-General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
-such as ethernet controllers to processors using the TI GPMC as a data bus.
-
-Ethernet controllers connected to TI GPMC are represented as child nodes of
-the GPMC controller with an "ethernet" name.
-
-All timing relevant properties as well as generic GPMC child properties are
-explained in a separate documents. Please refer to
-Documentation/devicetree/bindings/bus/ti-gpmc.txt
-
-For the properties relevant to the ethernet controller connected to the GPMC
-refer to the binding documentation of the device. For example, the documentation
-for the SMSC 911x is Documentation/devicetree/bindings/net/smsc911x.txt
-
-Child nodes need to specify the GPMC bus address width using the "bank-width"
-property but is possible that an ethernet controller also has a property to
-specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
-address width, it supports devices with 32-bit word registers.
-For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
-OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
-
-Required properties:
-- bank-width: Address width of the device in bytes. GPMC supports 8-bit
- and 16-bit devices and so must be either 1 or 2 bytes.
-- compatible: Compatible string property for the ethernet child device.
-- gpmc,cs-on: Chip-select assertion time
-- gpmc,cs-rd-off: Chip-select de-assertion time for reads
-- gpmc,cs-wr-off: Chip-select de-assertion time for writes
-- gpmc,oe-on: Output-enable assertion time
-- gpmc,oe-off Output-enable de-assertion time
-- gpmc,we-on: Write-enable assertion time
-- gpmc,we-off: Write-enable de-assertion time
-- gpmc,access: Start cycle to first data capture (read access)
-- gpmc,rd-cycle: Total read cycle time
-- gpmc,wr-cycle: Total write cycle time
-- reg: Chip-select, base address (relative to chip-select)
- and size of the memory mapped for the device.
- Note that base address will be typically 0 as this
- is the start of the chip-select.
-
-Optional properties:
-- gpmc,XXX Additional GPMC timings and settings parameters. See
- Documentation/devicetree/bindings/bus/ti-gpmc.txt
-
-Example:
-
-gpmc: gpmc@6e000000 {
- compatible = "ti,omap3430-gpmc";
- ti,hwmods = "gpmc";
- reg = <0x6e000000 0x1000>;
- interrupts = <20>;
- gpmc,num-cs = <8>;
- gpmc,num-waitpins = <4>;
- #address-cells = <2>;
- #size-cells = <1>;
-
- ranges = <5 0 0x2c000000 0x1000000>;
-
- ethernet@5,0 {
- compatible = "smsc,lan9221", "smsc,lan9115";
- reg = <5 0 0xff>;
- bank-width = <2>;
-
- gpmc,mux-add-data;
- gpmc,cs-on = <0>;
- gpmc,cs-rd-off = <186>;
- gpmc,cs-wr-off = <186>;
- gpmc,adv-on = <12>;
- gpmc,adv-rd-off = <48>;
- gpmc,adv-wr-off = <48>;
- gpmc,oe-on = <54>;
- gpmc,oe-off = <168>;
- gpmc,we-on = <54>;
- gpmc,we-off = <168>;
- gpmc,rd-cycle = <186>;
- gpmc,wr-cycle = <186>;
- gpmc,access = <114>;
- gpmc,page-burst-access = <6>;
- gpmc,bus-turnaround = <12>;
- gpmc,cycle2cycle-delay = <18>;
- gpmc,wr-data-mux-bus = <90>;
- gpmc,wr-access = <186>;
- gpmc,cycle2cycle-samecsen;
- gpmc,cycle2cycle-diffcsen;
-
- interrupt-parent = <&gpio6>;
- interrupts = <16>;
- vmmc-supply = <&vddvario>;
- vmmc_aux-supply = <&vdd33a>;
- reg-io-width = <4>;
-
- smsc,save-mac-address;
- };
-};
diff --git a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt b/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
deleted file mode 100644
index b3aa90f0ce44..000000000000
--- a/trunk/Documentation/devicetree/bindings/pinctrl/pinctrl-vt8500.txt
+++ /dev/null
@@ -1,57 +0,0 @@
-VIA VT8500 and Wondermedia WM8xxx-series pinmux/gpio controller
-
-These SoCs contain a combined Pinmux/GPIO module. Each pin may operate as
-either a GPIO in, GPIO out or as an alternate function (I2C, SPI etc).
-
-Required properties:
-- compatible: "via,vt8500-pinctrl", "wm,wm8505-pinctrl", "wm,wm8650-pinctrl",
- "wm8750-pinctrl" or "wm,wm8850-pinctrl"
-- reg: Should contain the physical address of the module's registers.
-- interrupt-controller: Marks the device node as an interrupt controller.
-- #interrupt-cells: Should be two.
-- gpio-controller: Marks the device node as a GPIO controller.
-- #gpio-cells : Should be two. The first cell is the pin number and the
- second cell is used to specify optional parameters.
- bit 0 - active low
-
-Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
-
-Please refer to pinctrl-bindings.txt in this directory for details of the
-common pinctrl bindings used by client devices, including the meaning of the
-phrase "pin configuration node".
-
-Each pin configuration node lists the pin(s) to which it applies, and one or
-more of the mux functions to select on those pin(s), and pull-up/down
-configuration. Each subnode only affects those parameters that are explicitly
-listed. In other words, a subnode that lists only a mux function implies no
-information about any pull configuration. Similarly, a subnode that lists only
-a pull parameter implies no information about the mux function.
-
-Required subnode-properties:
-- wm,pins: An array of cells. Each cell contains the ID of a pin.
-
-Optional subnode-properties:
-- wm,function: Integer, containing the function to mux to the pin(s):
- 0: GPIO in
- 1: GPIO out
- 2: alternate
-
-- wm,pull: Integer, representing the pull-down/up to apply to the pin(s):
- 0: none
- 1: down
- 2: up
-
-Each of wm,function and wm,pull may contain either a single value which
-will be applied to all pins in wm,pins, or one value for each entry in
-wm,pins.
-
-Example:
-
- pinctrl: pinctrl {
- compatible = "wm,wm8505-pinctrl";
- reg = <0xD8110000 0x10000>;
- interrupt-controller;
- #interrupt-cells = <2>;
- gpio-controller;
- #gpio-cells = <2>;
- };
diff --git a/trunk/Documentation/devicetree/bindings/reset/reset.txt b/trunk/Documentation/devicetree/bindings/reset/reset.txt
deleted file mode 100644
index 31db6ff84908..000000000000
--- a/trunk/Documentation/devicetree/bindings/reset/reset.txt
+++ /dev/null
@@ -1,75 +0,0 @@
-= Reset Signal Device Tree Bindings =
-
-This binding is intended to represent the hardware reset signals present
-internally in most IC (SoC, FPGA, ...) designs. Reset signals for whole
-standalone chips are most likely better represented as GPIOs, although there
-are likely to be exceptions to this rule.
-
-Hardware blocks typically receive a reset signal. This signal is generated by
-a reset provider (e.g. power management or clock module) and received by a
-reset consumer (the module being reset, or a module managing when a sub-
-ordinate module is reset). This binding exists to represent the provider and
-consumer, and provide a way to couple the two together.
-
-A reset signal is represented by the phandle of the provider, plus a reset
-specifier - a list of DT cells that represents the reset signal within the
-provider. The length (number of cells) and semantics of the reset specifier
-are dictated by the binding of the reset provider, although common schemes
-are described below.
-
-A word on where to place reset signal consumers in device tree: It is possible
-in hardware for a reset signal to affect multiple logically separate HW blocks
-at once. In this case, it would be unwise to represent this reset signal in
-the DT node of each affected HW block, since if activated, an unrelated block
-may be reset. Instead, reset signals should be represented in the DT node
-where it makes most sense to control it; this may be a bus node if all
-children of the bus are affected by the reset signal, or an individual HW
-block node for dedicated reset signals. The intent of this binding is to give
-appropriate software access to the reset signals in order to manage the HW,
-rather than to slavishly enumerate the reset signal that affects each HW
-block.
-
-= Reset providers =
-
-Required properties:
-#reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
- with a single reset output and 1 for nodes with multiple
- reset outputs.
-
-For example:
-
- rst: reset-controller {
- #reset-cells = <1>;
- };
-
-= Reset consumers =
-
-Required properties:
-resets: List of phandle and reset specifier pairs, one pair
- for each reset signal that affects the device, or that the
- device manages. Note: if the reset provider specifies '0' for
- #reset-cells, then only the phandle portion of the pair will
- appear.
-
-Optional properties:
-reset-names: List of reset signal name strings sorted in the same order as
- the resets property. Consumers drivers will use reset-names to
- match reset signal names with reset specifiers.
-
-For example:
-
- device {
- resets = <&rst 20>;
- reset-names = "reset";
- };
-
-This represents a device with a single reset signal named "reset".
-
- bus {
- resets = <&rst 10> <&rst 11> <&rst 12> <&rst 11>;
- reset-names = "i2s1", "i2s2", "dma", "mixer";
- };
-
-This represents a bus that controls the reset signal of each of four sub-
-ordinate devices. Consider for example a bus that fails to operate unless no
-child device has reset asserted.
diff --git a/trunk/Documentation/devicetree/bindings/sound/ak5386.txt b/trunk/Documentation/devicetree/bindings/sound/ak5386.txt
deleted file mode 100644
index dc3914fe6ce8..000000000000
--- a/trunk/Documentation/devicetree/bindings/sound/ak5386.txt
+++ /dev/null
@@ -1,19 +0,0 @@
-AK5386 Single-ended 24-Bit 192kHz delta-sigma ADC
-
-This device has no control interface.
-
-Required properties:
-
- - compatible : "asahi-kasei,ak5386"
-
-Optional properties:
-
- - reset-gpio : a GPIO spec for the reset/power down pin.
- If specified, it will be deasserted at probe time.
-
-Example:
-
-spdif: ak5386@0 {
- compatible = "asahi-kasei,ak5386";
- reset-gpio = <&gpio0 23>;
-};
diff --git a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
index 0e5c12c66523..1ac7b1642186 100644
--- a/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
+++ b/trunk/Documentation/devicetree/bindings/sound/nvidia,tegra30-ahub.txt
@@ -1,22 +1,12 @@
NVIDIA Tegra30 AHUB (Audio Hub)
Required properties:
-- compatible : "nvidia,tegra30-ahub", "nvidia,tegra114-ahub", etc.
+- compatible : "nvidia,tegra30-ahub"
- reg : Should contain the register physical address and length for each of
- the AHUB's register blocks.
- - Tegra30 requires 2 entries, for the APBIF and AHUB/AUDIO register blocks.
- - Tegra114 requires an additional entry, for the APBIF2 register block.
+ the AHUB's APBIF registers and the AHUB's own registers.
- interrupts : Should contain AHUB interrupt
-- nvidia,dma-request-selector : A list of the DMA channel specifiers. Each
- entry contains the Tegra DMA controller's phandle and request selector.
- If a single entry is present, the request selectors for the channels are
- assumed to be contiguous, and increment from this value.
- If multiple values are given, one value must be given per channel.
-- clocks : Must contain an entry for each required entry in clock-names.
-- clock-names : Must include the following entries:
- - Tegra30: Requires d_audio, apbif, i2s0, i2s1, i2s2, i2s3, i2s4, dam0,
- dam1, dam2, spdif_in.
- - Tegra114: Additionally requires amx, adx.
+- nvidia,dma-request-selector : The Tegra DMA controller's phandle and
+ request selector for the first APBIF channel.
- ranges : The bus address mapping for the configlink register bus.
Can be empty since the mapping is 1:1.
- #address-cells : For the configlink bus. Should be <1>;
@@ -35,13 +25,7 @@ ahub@70080000 {
reg = <0x70080000 0x200 0x70080200 0x100>;
interrupts = < 0 103 0x04 >;
nvidia,dma-request-selector = <&apbdma 1>;
- clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
- <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
- <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
- <&tegra_car 110>, <&tegra_car 162>;
- clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
- "i2s3", "i2s4", "dam0", "dam1", "dam2",
- "spdif_in";
+
ranges;
#address-cells = <1>;
#size-cells = <1>;
diff --git a/trunk/Documentation/devicetree/bindings/sound/ti,tas5086.txt b/trunk/Documentation/devicetree/bindings/sound/ti,tas5086.txt
deleted file mode 100644
index 8ea4f5b4818d..000000000000
--- a/trunk/Documentation/devicetree/bindings/sound/ti,tas5086.txt
+++ /dev/null
@@ -1,32 +0,0 @@
-Texas Instruments TAS5086 6-channel PWM Processor
-
-Required properties:
-
- - compatible: Should contain "ti,tas5086".
- - reg: The i2c address. Should contain <0x1b>.
-
-Optional properties:
-
- - reset-gpio: A GPIO spec to define which pin is connected to the
- chip's !RESET pin. If specified, the driver will
- assert a hardware reset at probe time.
-
- - ti,charge-period: This property should contain the time in microseconds
- that closely matches the external single-ended
- split-capacitor charge period. The hardware chip
- waits for this period of time before starting the
- PWM signals. This helps reduce pops and clicks.
-
- When not specified, the hardware default of 1300ms
- is retained.
-
-Examples:
-
- i2c_bus {
- tas5086@1b {
- compatible = "ti,tas5086";
- reg = <0x1b>;
- reset-gpio = <&gpio 23 0>;
- ti,charge-period = <156000>;
- };
- };
diff --git a/trunk/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt b/trunk/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
deleted file mode 100644
index 993695c659e1..000000000000
--- a/trunk/Documentation/devicetree/bindings/timer/cadence,ttc-timer.txt
+++ /dev/null
@@ -1,17 +0,0 @@
-Cadence TTC - Triple Timer Counter
-
-Required properties:
-- compatible : Should be "cdns,ttc".
-- reg : Specifies base physical address and size of the registers.
-- interrupts : A list of 3 interrupts; one per timer channel.
-- clocks: phandle to the source clock
-
-Example:
-
-ttc0: ttc0@f8001000 {
- interrupt-parent = <&intc>;
- interrupts = < 0 10 4 0 11 4 0 12 4 >;
- compatible = "cdns,ttc";
- reg = <0xF8001000 0x1000>;
- clocks = <&cpu_clk 3>;
-};
diff --git a/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt b/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
deleted file mode 100644
index cb47bfbcaeea..000000000000
--- a/trunk/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-Samsung's Multi Core Timer (MCT)
-
-The Samsung's Multi Core Timer (MCT) module includes two main blocks, the
-global timer and CPU local timers. The global timer is a 64-bit free running
-up-counter and can generate 4 interrupts when the counter reaches one of the
-four preset counter values. The CPU local timers are 32-bit free running
-down-counters and generate an interrupt when the counter expires. There is
-one CPU local timer instantiated in MCT for every CPU in the system.
-
-Required properties:
-
-- compatible: should be "samsung,exynos4210-mct".
- (a) "samsung,exynos4210-mct", for mct compatible with Exynos4210 mct.
- (b) "samsung,exynos4412-mct", for mct compatible with Exynos4412 mct.
-
-- reg: base address of the mct controller and length of the address space
- it occupies.
-
-- interrupts: the list of interrupts generated by the controller. The following
- should be the order of the interrupts specified. The local timer interrupts
- should be specified after the four global timer interrupts have been
- specified.
-
- 0: Global Timer Interrupt 0
- 1: Global Timer Interrupt 1
- 2: Global Timer Interrupt 2
- 3: Global Timer Interrupt 3
- 4: Local Timer Interrupt 0
- 5: Local Timer Interrupt 1
- 6: ..
- 7: ..
- i: Local Timer Interrupt n
-
-Example 1: In this example, the system uses only the first global timer
- interrupt generated by MCT and the remaining three global timer
- interrupts are unused. Two local timer interrupts have been
- specified.
-
- mct@10050000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x10050000 0x800>;
- interrupts = <0 57 0>, <0 0 0>, <0 0 0>, <0 0 0>,
- <0 42 0>, <0 48 0>;
- };
-
-Example 2: In this example, the MCT global and local timer interrupts are
- connected to two seperate interrupt controllers. Hence, an
- interrupt-map is created to map the interrupts to the respective
- interrupt controllers.
-
- mct@101C0000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x101C0000 0x800>;
- interrupt-controller;
- #interrups-cells = <2>;
- interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
- <4 0>, <5 0>;
-
- mct_map: mct-map {
- #interrupt-cells = <2>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0x0 0 &combiner 23 3>,
- <0x4 0 &gic 0 120 0>,
- <0x5 0 &gic 0 121 0>;
- };
- };
diff --git a/trunk/Documentation/devicetree/bindings/usb/exynos-usb.txt b/trunk/Documentation/devicetree/bindings/usb/exynos-usb.txt
deleted file mode 100644
index f66fcddba46f..000000000000
--- a/trunk/Documentation/devicetree/bindings/usb/exynos-usb.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Samsung Exynos SoC USB controller
-
-The USB devices interface with USB controllers on Exynos SOCs.
-The device node has following properties.
-
-EHCI
-Required properties:
- - compatible: should be "samsung,exynos4210-ehci" for USB 2.0
- EHCI controller in host mode.
- - reg: physical base address of the controller and length of memory mapped
- region.
- - interrupts: interrupt number to the cpu.
-
-Optional properties:
- - samsung,vbus-gpio: if present, specifies the GPIO that
- needs to be pulled up for the bus to be powered.
-
-Example:
-
- usb@12110000 {
- compatible = "samsung,exynos4210-ehci";
- reg = <0x12110000 0x100>;
- interrupts = <0 71 0>;
- samsung,vbus-gpio = <&gpx2 6 1 3 3>;
- };
-
-OHCI
-Required properties:
- - compatible: should be "samsung,exynos4210-ohci" for USB 2.0
- OHCI companion controller in host mode.
- - reg: physical base address of the controller and length of memory mapped
- region.
- - interrupts: interrupt number to the cpu.
-
-Example:
- usb@12120000 {
- compatible = "samsung,exynos4210-ohci";
- reg = <0x12120000 0x100>;
- interrupts = <0 71 0>;
- };
diff --git a/trunk/Documentation/filesystems/nfs/00-INDEX b/trunk/Documentation/filesystems/nfs/00-INDEX
index 66eb6c8c5334..1716874a651e 100644
--- a/trunk/Documentation/filesystems/nfs/00-INDEX
+++ b/trunk/Documentation/filesystems/nfs/00-INDEX
@@ -20,5 +20,3 @@ rpc-cache.txt
- introduction to the caching mechanisms in the sunrpc layer.
idmapper.txt
- information for configuring request-keys to be used by idmapper
-knfsd-rpcgss.txt
- - Information on GSS authentication support in the NFS Server
diff --git a/trunk/Documentation/filesystems/nfs/rpc-server-gss.txt b/trunk/Documentation/filesystems/nfs/rpc-server-gss.txt
deleted file mode 100644
index 716f4be8e8b3..000000000000
--- a/trunk/Documentation/filesystems/nfs/rpc-server-gss.txt
+++ /dev/null
@@ -1,91 +0,0 @@
-
-rpcsec_gss support for kernel RPC servers
-=========================================
-
-This document gives references to the standards and protocols used to
-implement RPCGSS authentication in kernel RPC servers such as the NFS
-server and the NFS client's NFSv4.0 callback server. (But note that
-NFSv4.1 and higher don't require the client to act as a server for the
-purposes of authentication.)
-
-RPCGSS is specified in a few IETF documents:
- - RFC2203 v1: http://tools.ietf.org/rfc/rfc2203.txt
- - RFC5403 v2: http://tools.ietf.org/rfc/rfc5403.txt
-and there is a 3rd version being proposed:
- - http://tools.ietf.org/id/draft-williams-rpcsecgssv3.txt
- (At draft n. 02 at the time of writing)
-
-Background
-----------
-
-The RPCGSS Authentication method describes a way to perform GSSAPI
-Authentication for NFS. Although GSSAPI is itself completely mechanism
-agnostic, in many cases only the KRB5 mechanism is supported by NFS
-implementations.
-
-The Linux kernel, at the moment, supports only the KRB5 mechanism, and
-depends on GSSAPI extensions that are KRB5 specific.
-
-GSSAPI is a complex library, and implementing it completely in kernel is
-unwarranted. However GSSAPI operations are fundementally separable in 2
-parts:
-- initial context establishment
-- integrity/privacy protection (signing and encrypting of individual
- packets)
-
-The former is more complex and policy-independent, but less
-performance-sensitive. The latter is simpler and needs to be very fast.
-
-Therefore, we perform per-packet integrity and privacy protection in the
-kernel, but leave the initial context establishment to userspace. We
-need upcalls to request userspace to perform context establishment.
-
-NFS Server Legacy Upcall Mechanism
-----------------------------------
-
-The classic upcall mechanism uses a custom text based upcall mechanism
-to talk to a custom daemon called rpc.svcgssd that is provide by the
-nfs-utils package.
-
-This upcall mechanism has 2 limitations:
-
-A) It can handle tokens that are no bigger than 2KiB
-
-In some Kerberos deployment GSSAPI tokens can be quite big, up and
-beyond 64KiB in size due to various authorization extensions attacked to
-the Kerberos tickets, that needs to be sent through the GSS layer in
-order to perform context establishment.
-
-B) It does not properly handle creds where the user is member of more
-than a few housand groups (the current hard limit in the kernel is 65K
-groups) due to limitation on the size of the buffer that can be send
-back to the kernel (4KiB).
-
-NFS Server New RPC Upcall Mechanism
------------------------------------
-
-The newer upcall mechanism uses RPC over a unix socket to a daemon
-called gss-proxy, implemented by a userspace program called Gssproxy.
-
-The gss_proxy RPC protocol is currently documented here:
-
- https://fedorahosted.org/gss-proxy/wiki/ProtocolDocumentation
-
-This upcall mechanism uses the kernel rpc client and connects to the gssproxy
-userspace program over a regular unix socket. The gssproxy protocol does not
-suffer from the size limitations of the legacy protocol.
-
-Negotiating Upcall Mechanisms
------------------------------
-
-To provide backward compatibility, the kernel defaults to using the
-legacy mechanism. To switch to the new mechanism, gss-proxy must bind
-to /var/run/gssproxy.sock and then write "1" to
-/proc/net/rpc/use-gss-proxy. If gss-proxy dies, it must repeat both
-steps.
-
-Once the upcall mechanism is chosen, it cannot be changed. To prevent
-locking into the legacy mechanisms, the above steps must be performed
-before starting nfsd. Whoever starts nfsd can guarantee this by reading
-from /proc/net/rpc/use-gss-proxy and checking that it contains a
-"1"--the read will block until gss-proxy has done its write to the file.
diff --git a/trunk/Documentation/sound/alsa/HD-Audio.txt b/trunk/Documentation/sound/alsa/HD-Audio.txt
index c3c912d023cc..d4faa63ff352 100644
--- a/trunk/Documentation/sound/alsa/HD-Audio.txt
+++ b/trunk/Documentation/sound/alsa/HD-Audio.txt
@@ -461,13 +461,11 @@ The generic parser supports the following hints:
the corresponding mixer control, if available
- add_stereo_mix_input (bool): add the stereo mix (analog-loopback
mix) to the input mux if available
-- add_jack_modes (bool): add "xxx Jack Mode" enum controls to each
- I/O jack for allowing to change the headphone amp and mic bias VREF
- capabilities
+- add_out_jack_modes (bool): add "xxx Jack Mode" enum controls to each
+ output jack for allowing to change the headphone amp capability
+- add_in_jack_modes (bool): add "xxx Jack Mode" enum controls to each
+ input jack for allowing to change the mic bias vref
- power_down_unused (bool): power down the unused widgets
-- add_hp_mic (bool): add the headphone to capture source if possible
-- hp_mic_detect (bool): enable/disable the hp/mic shared input for a
- single built-in mic case; default true
- mixer_nid (int): specifies the widget NID of the analog-loopback
mixer
diff --git a/trunk/arch/arm/Kconfig b/trunk/arch/arm/Kconfig
index 1e31dac36a5f..4ed24b4aa714 100644
--- a/trunk/arch/arm/Kconfig
+++ b/trunk/arch/arm/Kconfig
@@ -59,7 +59,6 @@ config ARM
select CLONE_BACKWARDS
select OLD_SIGSUSPEND3
select OLD_SIGACTION
- select HAVE_CONTEXT_TRACKING
help
The ARM series is a line of low-power-consumption RISC chip designs
licensed by ARM Ltd and targeted at embedded applications and
@@ -689,15 +688,12 @@ config ARCH_SA1100
config ARCH_S3C24XX
bool "Samsung S3C24XX SoCs"
select ARCH_HAS_CPUFREQ
- select ARCH_REQUIRE_GPIOLIB
+ select ARCH_USES_GETTIMEOFFSET
select CLKDEV_LOOKUP
- select CLKSRC_MMIO
- select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
select HAVE_S3C_RTC if RTC_CLASS
- select MULTI_IRQ_HANDLER
select NEED_MACH_GPIO_H
select NEED_MACH_IO_H
help
@@ -710,11 +706,10 @@ config ARCH_S3C64XX
bool "Samsung S3C64XX"
select ARCH_HAS_CPUFREQ
select ARCH_REQUIRE_GPIOLIB
+ select ARCH_USES_GETTIMEOFFSET
select ARM_VIC
select CLKDEV_LOOKUP
- select CLKSRC_MMIO
select CPU_V6
- select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -748,11 +743,9 @@ config ARCH_S5P64X0
config ARCH_S5PC100
bool "Samsung S5PC100"
- select ARCH_REQUIRE_GPIOLIB
+ select ARCH_USES_GETTIMEOFFSET
select CLKDEV_LOOKUP
- select CLKSRC_MMIO
select CPU_V7
- select GENERIC_CLOCKEVENTS
select HAVE_CLK
select HAVE_S3C2410_I2C if I2C
select HAVE_S3C2410_WATCHDOG if WATCHDOG
@@ -785,7 +778,6 @@ config ARCH_EXYNOS
select ARCH_HAS_HOLES_MEMORYMODEL
select ARCH_SPARSEMEM_ENABLE
select CLKDEV_LOOKUP
- select COMMON_CLK
select CPU_V7
select GENERIC_CLOCKEVENTS
select HAVE_CLK
@@ -1487,14 +1479,6 @@ config HAVE_ARM_TWD
help
This options enables support for the ARM timer and watchdog unit
-config MCPM
- bool "Multi-Cluster Power Management"
- depends on CPU_V7 && SMP
- help
- This option provides the common power management infrastructure
- for (multi-)cluster based systems, such as big.LITTLE based
- systems.
-
choice
prompt "Memory split"
default VMSPLIT_3G
@@ -1559,8 +1543,7 @@ config ARCH_NR_GPIO
default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
default 512 if SOC_OMAP5
default 392 if ARCH_U8500
- default 352 if ARCH_VT8500
- default 288 if ARCH_SUNXI
+ default 288 if ARCH_VT8500 || ARCH_SUNXI
default 264 if MACH_H4700
default 0
help
@@ -1582,9 +1565,8 @@ config SCHED_HRTICK
def_bool HIGH_RES_TIMERS
config THUMB2_KERNEL
- bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
+ bool "Compile the kernel in Thumb-2 mode"
depends on CPU_V7 && !CPU_V6 && !CPU_V6K
- default y if CPU_THUMBONLY
select AEABI
select ARM_ASM_UNIFIED
select ARM_UNWIND
diff --git a/trunk/arch/arm/Kconfig.debug b/trunk/arch/arm/Kconfig.debug
index f57a6ba26e04..54d6fdc03e04 100644
--- a/trunk/arch/arm/Kconfig.debug
+++ b/trunk/arch/arm/Kconfig.debug
@@ -330,13 +330,6 @@ choice
Say Y here if you want kernel low-level debugging support
on PicoXcell based platforms.
- config DEBUG_PXA_UART1
- depends on ARCH_PXA
- bool "Use PXA UART1 for low-level debug"
- help
- Say Y here if you want kernel low-level debugging support
- on PXA UART1.
-
config DEBUG_REALVIEW_STD_PORT
bool "RealView Default UART"
depends on ARCH_REALVIEW
@@ -622,7 +615,6 @@ config DEBUG_LL_INCLUDE
default "debug/bcm2835.S" if DEBUG_BCM2835
default "debug/cns3xxx.S" if DEBUG_CNS3XXX
default "debug/exynos.S" if DEBUG_EXYNOS_UART
- default "debug/highbank.S" if DEBUG_HIGHBANK_UART
default "debug/icedcc.S" if DEBUG_ICEDCC
default "debug/imx.S" if DEBUG_IMX1_UART || \
DEBUG_IMX25_UART || \
@@ -632,35 +624,23 @@ config DEBUG_LL_INCLUDE
DEBUG_IMX51_UART || \
DEBUG_IMX53_UART ||\
DEBUG_IMX6Q_UART
+ default "debug/highbank.S" if DEBUG_HIGHBANK_UART
default "debug/mvebu.S" if DEBUG_MVEBU_UART
default "debug/mxs.S" if DEBUG_IMX23_UART || DEBUG_IMX28_UART
default "debug/nomadik.S" if DEBUG_NOMADIK_UART
default "debug/omap2plus.S" if DEBUG_OMAP2PLUS_UART
default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
- default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \
- DEBUG_MMP_UART3
default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
- default "debug/tegra.S" if DEBUG_TEGRA_UART
- default "debug/ux500.S" if DEBUG_UX500_UART
default "debug/vexpress.S" if DEBUG_VEXPRESS_UART0_DETECT || \
DEBUG_VEXPRESS_UART0_CA9 || DEBUG_VEXPRESS_UART0_RS1
default "debug/vt8500.S" if DEBUG_VT8500_UART0
+ default "debug/tegra.S" if DEBUG_TEGRA_UART
+ default "debug/ux500.S" if DEBUG_UX500_UART
default "debug/zynq.S" if DEBUG_ZYNQ_UART0 || DEBUG_ZYNQ_UART1
default "mach/debug-macro.S"
-config DEBUG_UNCOMPRESS
- bool
- default y if ARCH_MULTIPLATFORM && DEBUG_LL && \
- !DEBUG_OMAP2PLUS_UART && \
- !DEBUG_TEGRA_UART
-
-config UNCOMPRESS_INCLUDE
- string
- default "debug/uncompress.h" if ARCH_MULTIPLATFORM
- default "mach/uncompress.h"
-
config EARLY_PRINTK
bool "Early printk"
depends on DEBUG_LL
diff --git a/trunk/arch/arm/boot/compressed/Makefile b/trunk/arch/arm/boot/compressed/Makefile
index 3580d57ea218..afed28e37ea5 100644
--- a/trunk/arch/arm/boot/compressed/Makefile
+++ b/trunk/arch/arm/boot/compressed/Makefile
@@ -24,9 +24,6 @@ endif
AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
HEAD = head.o
OBJS += misc.o decompress.o
-ifeq ($(CONFIG_DEBUG_UNCOMPRESS),y)
-OBJS += debug.o
-endif
FONTC = $(srctree)/drivers/video/console/font_acorn_8x8.c
# string library code (-Os is enforced to keep it much smaller)
diff --git a/trunk/arch/arm/boot/compressed/debug.S b/trunk/arch/arm/boot/compressed/debug.S
deleted file mode 100644
index 6e8382d5b7a4..000000000000
--- a/trunk/arch/arm/boot/compressed/debug.S
+++ /dev/null
@@ -1,12 +0,0 @@
-#include
-#include
-
-#include CONFIG_DEBUG_LL_INCLUDE
-
-ENTRY(putc)
- addruart r1, r2, r3
- waituart r3, r1
- senduart r0, r1
- busyuart r3, r1
- mov pc, lr
-ENDPROC(putc)
diff --git a/trunk/arch/arm/boot/compressed/misc.c b/trunk/arch/arm/boot/compressed/misc.c
index 31bd43b82095..df899834d84e 100644
--- a/trunk/arch/arm/boot/compressed/misc.c
+++ b/trunk/arch/arm/boot/compressed/misc.c
@@ -25,7 +25,13 @@ unsigned int __machine_arch_type;
static void putstr(const char *ptr);
extern void error(char *x);
-#include CONFIG_UNCOMPRESS_INCLUDE
+#ifdef CONFIG_ARCH_MULTIPLATFORM
+static inline void putc(int c) {}
+static inline void flush(void) {}
+static inline void arch_decomp_setup(void) {}
+#else
+#include
+#endif
#ifdef CONFIG_DEBUG_ICEDCC
diff --git a/trunk/arch/arm/boot/dts/Makefile b/trunk/arch/arm/boot/dts/Makefile
index 853e199ea89f..20358fb43450 100644
--- a/trunk/arch/arm/boot/dts/Makefile
+++ b/trunk/arch/arm/boot/dts/Makefile
@@ -49,10 +49,7 @@ dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
exynos4210-smdkv310.dtb \
exynos4210-trats.dtb \
- exynos4412-odroidx.dtb \
exynos4412-smdk4412.dtb \
- exynos4412-origen.dtb \
- exynos5250-arndale.dtb \
exynos5250-smdk5250.dtb \
exynos5250-snow.dtb \
exynos5440-ssdk5440.dtb
@@ -61,8 +58,7 @@ dtb-$(CONFIG_ARCH_HIGHBANK) += highbank.dtb \
dtb-$(CONFIG_ARCH_INTEGRATOR) += integratorap.dtb \
integratorcp.dtb
dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
-dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
- kirkwood-dns320.dtb \
+dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
kirkwood-dns325.dtb \
kirkwood-dockstar.dtb \
kirkwood-dreamplug.dtb \
@@ -76,7 +72,6 @@ dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-cloudbox.dtb \
kirkwood-lschlv2.dtb \
kirkwood-lsxhl.dtb \
kirkwood-mplcec4.dtb \
- kirkwood-netgear_readynas_duo_v2.dtb \
kirkwood-ns2.dtb \
kirkwood-ns2lite.dtb \
kirkwood-ns2max.dtb \
@@ -155,9 +150,7 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
ccu9540.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
r8a7740-armadillo800eva.dtb \
- r8a7779-marzen-reference.dtb \
sh73a0-kzm9g.dtb \
- sh73a0-kzm9g-reference.dtb \
sh7372-mackerel.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
socfpga_vt.dtb
diff --git a/trunk/arch/arm/boot/dts/bcm11351.dtsi b/trunk/arch/arm/boot/dts/bcm11351.dtsi
index 41b2c6c33f09..8f71f40722b9 100644
--- a/trunk/arch/arm/boot/dts/bcm11351.dtsi
+++ b/trunk/arch/arm/boot/dts/bcm11351.dtsi
@@ -31,11 +31,6 @@
<0x3ff00100 0x100>;
};
- smc@0x3404c000 {
- compatible = "bcm,bcm11351-smc", "bcm,kona-smc";
- reg = <0x3404c000 0x400>; //1 KiB in SRAM
- };
-
uart@3e000000 {
compatible = "bcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
status = "disabled";
diff --git a/trunk/arch/arm/boot/dts/cros5250-common.dtsi b/trunk/arch/arm/boot/dts/cros5250-common.dtsi
index 62eceb4f0d3f..46c098017036 100644
--- a/trunk/arch/arm/boot/dts/cros5250-common.dtsi
+++ b/trunk/arch/arm/boot/dts/cros5250-common.dtsi
@@ -24,144 +24,6 @@
samsung,i2c-max-bus-freq = <378000>;
gpios = <&gpb3 0 2 3 0>,
<&gpb3 1 2 3 0>;
-
- max77686@09 {
- compatible = "maxim,max77686";
- reg = <0x09>;
-
- voltage-regulators {
- ldo1_reg: LDO1 {
- regulator-name = "P1.0V_LDO_OUT1";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "P1.8V_LDO_OUT2";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "P1.8V_LDO_OUT3";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo7_reg: LDO7 {
- regulator-name = "P1.1V_LDO_OUT7";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- };
-
- ldo8_reg: LDO8 {
- regulator-name = "P1.0V_LDO_OUT8";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- ldo10_reg: LDO10 {
- regulator-name = "P1.8V_LDO_OUT10";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo12_reg: LDO12 {
- regulator-name = "P3.0V_LDO_OUT12";
- regulator-min-microvolt = <3000000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- };
-
- ldo14_reg: LDO14 {
- regulator-name = "P1.8V_LDO_OUT14";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- ldo15_reg: LDO15 {
- regulator-name = "P1.0V_LDO_OUT15";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- };
-
- ldo16_reg: LDO16 {
- regulator-name = "P1.8V_LDO_OUT16";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- buck1_reg: BUCK1 {
- regulator-name = "vdd_mif";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- buck3_reg: BUCK3 {
- regulator-name = "vdd_int";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- buck4_reg: BUCK4 {
- regulator-name = "vdd_g3d";
- regulator-min-microvolt = <850000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- buck5_reg: BUCK5 {
- regulator-name = "P1.8V_BUCK_OUT5";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- buck6_reg: BUCK6 {
- regulator-name = "P1.35V_BUCK_OUT6";
- regulator-min-microvolt = <1350000>;
- regulator-max-microvolt = <1350000>;
- regulator-always-on;
- };
-
- buck7_reg: BUCK7 {
- regulator-name = "P2.0V_BUCK_OUT7";
- regulator-min-microvolt = <2000000>;
- regulator-max-microvolt = <2000000>;
- regulator-always-on;
- };
-
- buck8_reg: BUCK8 {
- regulator-name = "P2.85V_BUCK_OUT8";
- regulator-min-microvolt = <2850000>;
- regulator-max-microvolt = <2850000>;
- regulator-always-on;
- };
- };
- };
};
i2c@12C70000 {
diff --git a/trunk/arch/arm/boot/dts/exynos4.dtsi b/trunk/arch/arm/boot/dts/exynos4.dtsi
index 9ac47d51c407..1a62bcf18aa3 100644
--- a/trunk/arch/arm/boot/dts/exynos4.dtsi
+++ b/trunk/arch/arm/boot/dts/exynos4.dtsi
@@ -86,8 +86,6 @@
compatible = "samsung,s3c2410-wdt";
reg = <0x10060000 0x100>;
interrupts = <0 43 0>;
- clocks = <&clock 345>;
- clock-names = "watchdog";
status = "disabled";
};
@@ -95,8 +93,6 @@
compatible = "samsung,s3c6410-rtc";
reg = <0x10070000 0x100>;
interrupts = <0 44 0>, <0 45 0>;
- clocks = <&clock 346>;
- clock-names = "rtc";
status = "disabled";
};
@@ -104,8 +100,6 @@
compatible = "samsung,s5pv210-keypad";
reg = <0x100A0000 0x100>;
interrupts = <0 109 0>;
- clocks = <&clock 347>;
- clock-names = "keypad";
status = "disabled";
};
@@ -113,8 +107,6 @@
compatible = "samsung,exynos4210-sdhci";
reg = <0x12510000 0x100>;
interrupts = <0 73 0>;
- clocks = <&clock 297>, <&clock 145>;
- clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
@@ -122,8 +114,6 @@
compatible = "samsung,exynos4210-sdhci";
reg = <0x12520000 0x100>;
interrupts = <0 74 0>;
- clocks = <&clock 298>, <&clock 146>;
- clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
@@ -131,8 +121,6 @@
compatible = "samsung,exynos4210-sdhci";
reg = <0x12530000 0x100>;
interrupts = <0 75 0>;
- clocks = <&clock 299>, <&clock 147>;
- clock-names = "hsmmc", "mmc_busclk.2";
status = "disabled";
};
@@ -140,16 +128,6 @@
compatible = "samsung,exynos4210-sdhci";
reg = <0x12540000 0x100>;
interrupts = <0 76 0>;
- clocks = <&clock 300>, <&clock 148>;
- clock-names = "hsmmc", "mmc_busclk.2";
- status = "disabled";
- };
-
- mfc: codec@13400000 {
- compatible = "samsung,mfc-v5";
- reg = <0x13400000 0x10000>;
- interrupts = <0 94 0>;
- samsung,power-domain = <&pd_mfc>;
status = "disabled";
};
@@ -157,8 +135,6 @@
compatible = "samsung,exynos4210-uart";
reg = <0x13800000 0x100>;
interrupts = <0 52 0>;
- clocks = <&clock 312>, <&clock 151>;
- clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
@@ -166,8 +142,6 @@
compatible = "samsung,exynos4210-uart";
reg = <0x13810000 0x100>;
interrupts = <0 53 0>;
- clocks = <&clock 313>, <&clock 152>;
- clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
@@ -175,8 +149,6 @@
compatible = "samsung,exynos4210-uart";
reg = <0x13820000 0x100>;
interrupts = <0 54 0>;
- clocks = <&clock 314>, <&clock 153>;
- clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
@@ -184,8 +156,6 @@
compatible = "samsung,exynos4210-uart";
reg = <0x13830000 0x100>;
interrupts = <0 55 0>;
- clocks = <&clock 315>, <&clock 154>;
- clock-names = "uart", "clk_uart_baud0";
status = "disabled";
};
@@ -195,8 +165,6 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x13860000 0x100>;
interrupts = <0 58 0>;
- clocks = <&clock 317>;
- clock-names = "i2c";
status = "disabled";
};
@@ -206,8 +174,6 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x13870000 0x100>;
interrupts = <0 59 0>;
- clocks = <&clock 318>;
- clock-names = "i2c";
status = "disabled";
};
@@ -217,8 +183,6 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x13880000 0x100>;
interrupts = <0 60 0>;
- clocks = <&clock 319>;
- clock-names = "i2c";
status = "disabled";
};
@@ -228,8 +192,6 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x13890000 0x100>;
interrupts = <0 61 0>;
- clocks = <&clock 320>;
- clock-names = "i2c";
status = "disabled";
};
@@ -239,8 +201,6 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x138A0000 0x100>;
interrupts = <0 62 0>;
- clocks = <&clock 321>;
- clock-names = "i2c";
status = "disabled";
};
@@ -250,8 +210,6 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x138B0000 0x100>;
interrupts = <0 63 0>;
- clocks = <&clock 322>;
- clock-names = "i2c";
status = "disabled";
};
@@ -261,8 +219,6 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x138C0000 0x100>;
interrupts = <0 64 0>;
- clocks = <&clock 323>;
- clock-names = "i2c";
status = "disabled";
};
@@ -272,8 +228,6 @@
compatible = "samsung,s3c2440-i2c";
reg = <0x138D0000 0x100>;
interrupts = <0 65 0>;
- clocks = <&clock 324>;
- clock-names = "i2c";
status = "disabled";
};
@@ -285,8 +239,6 @@
rx-dma-channel = <&pdma0 6>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 327>, <&clock 159>;
- clock-names = "spi", "spi_busclk0";
status = "disabled";
};
@@ -298,8 +250,6 @@
rx-dma-channel = <&pdma1 6>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 328>, <&clock 160>;
- clock-names = "spi", "spi_busclk0";
status = "disabled";
};
@@ -311,8 +261,6 @@
rx-dma-channel = <&pdma0 8>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 329>, <&clock 161>;
- clock-names = "spi", "spi_busclk0";
status = "disabled";
};
@@ -327,8 +275,6 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x12680000 0x1000>;
interrupts = <0 35 0>;
- clocks = <&clock 292>;
- clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
@@ -338,8 +284,6 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x12690000 0x1000>;
interrupts = <0 36 0>;
- clocks = <&clock 293>;
- clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
@@ -349,8 +293,6 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x12850000 0x1000>;
interrupts = <0 34 0>;
- clocks = <&clock 279>;
- clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
diff --git a/trunk/arch/arm/boot/dts/exynos4210-origen.dts b/trunk/arch/arm/boot/dts/exynos4210-origen.dts
index 1b30bc8e2654..f2710018e84e 100644
--- a/trunk/arch/arm/boot/dts/exynos4210-origen.dts
+++ b/trunk/arch/arm/boot/dts/exynos4210-origen.dts
@@ -57,12 +57,6 @@
status = "okay";
};
- codec@13400000 {
- samsung,mfc-r = <0x43000000 0x800000>;
- samsung,mfc-l = <0x51000000 0x800000>;
- status = "okay";
- };
-
serial@13800000 {
status = "okay";
};
@@ -127,16 +121,4 @@
linux,default-trigger = "heartbeat";
};
};
-
- fixed-rate-clocks {
- xxti {
- compatible = "samsung,clock-xxti";
- clock-frequency = <0>;
- };
-
- xusbxti {
- compatible = "samsung,clock-xusbxti";
- clock-frequency = <24000000>;
- };
- };
};
diff --git a/trunk/arch/arm/boot/dts/exynos4210-smdkv310.dts b/trunk/arch/arm/boot/dts/exynos4210-smdkv310.dts
index f52c86e2d424..f63490707f3a 100644
--- a/trunk/arch/arm/boot/dts/exynos4210-smdkv310.dts
+++ b/trunk/arch/arm/boot/dts/exynos4210-smdkv310.dts
@@ -43,12 +43,6 @@
status = "okay";
};
- codec@13400000 {
- samsung,mfc-r = <0x43000000 0x800000>;
- samsung,mfc-l = <0x51000000 0x800000>;
- status = "okay";
- };
-
serial@13800000 {
status = "okay";
};
@@ -195,16 +189,4 @@
};
};
};
-
- fixed-rate-clocks {
- xxti {
- compatible = "samsung,clock-xxti";
- clock-frequency = <12000000>;
- };
-
- xusbxti {
- compatible = "samsung,clock-xusbxti";
- clock-frequency = <24000000>;
- };
- };
};
diff --git a/trunk/arch/arm/boot/dts/exynos4210-trats.dts b/trunk/arch/arm/boot/dts/exynos4210-trats.dts
index 9a14484c7bb1..c346b64dff55 100644
--- a/trunk/arch/arm/boot/dts/exynos4210-trats.dts
+++ b/trunk/arch/arm/boot/dts/exynos4210-trats.dts
@@ -289,16 +289,4 @@
};
};
};
-
- fixed-rate-clocks {
- xxti {
- compatible = "samsung,clock-xxti";
- clock-frequency = <0>;
- };
-
- xusbxti {
- compatible = "samsung,clock-xusbxti";
- clock-frequency = <24000000>;
- };
- };
};
diff --git a/trunk/arch/arm/boot/dts/exynos4210.dtsi b/trunk/arch/arm/boot/dts/exynos4210.dtsi
index 15143bdbafb8..2feffc70814c 100644
--- a/trunk/arch/arm/boot/dts/exynos4210.dtsi
+++ b/trunk/arch/arm/boot/dts/exynos4210.dtsi
@@ -47,42 +47,6 @@
<0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>;
};
- mct@10050000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x10050000 0x800>;
- interrupt-controller;
- #interrups-cells = <2>;
- interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
- <4 0>, <5 0>;
- clocks = <&clock 3>, <&clock 344>;
- clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <2>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0x0 0 &gic 0 57 0>,
- <0x1 0 &gic 0 69 0>,
- <0x2 0 &combiner 12 6>,
- <0x3 0 &combiner 12 7>,
- <0x4 0 &gic 0 42 0>,
- <0x5 0 &gic 0 48 0>;
- };
- };
-
- clock: clock-controller@0x10030000 {
- compatible = "samsung,exynos4210-clock";
- reg = <0x10030000 0x20000>;
- #clock-cells = <1>;
- };
-
- pmu {
- compatible = "arm,cortex-a9-pmu";
- interrupt-parent = <&combiner>;
- interrupts = <2 2>, <3 2>;
- };
-
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4210-pinctrl";
reg = <0x11400000 0x1000>;
diff --git a/trunk/arch/arm/boot/dts/exynos4212.dtsi b/trunk/arch/arm/boot/dts/exynos4212.dtsi
index 36d4299789ef..c6ae2005961f 100644
--- a/trunk/arch/arm/boot/dts/exynos4212.dtsi
+++ b/trunk/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,26 +25,4 @@
gic:interrupt-controller@10490000 {
cpu-offset = <0x8000>;
};
-
- mct@10050000 {
- compatible = "samsung,exynos4412-mct";
- reg = <0x10050000 0x800>;
- interrupt-controller;
- #interrups-cells = <2>;
- interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
- <4 0>, <5 0>;
-
- mct_map: mct-map {
- #interrupt-cells = <2>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0x0 0 &gic 0 57 0>,
- <0x1 0 &combiner 12 5>,
- <0x2 0 &combiner 12 6>,
- <0x3 0 &combiner 12 7>,
- <0x4 0 &gic 1 12 0>,
- <0x5 0 &gic 1 12 0>;
- };
- };
};
diff --git a/trunk/arch/arm/boot/dts/exynos4412-odroidx.dts b/trunk/arch/arm/boot/dts/exynos4412-odroidx.dts
deleted file mode 100644
index 53bc8bf77984..000000000000
--- a/trunk/arch/arm/boot/dts/exynos4412-odroidx.dts
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * Hardkernel's Exynos4412 based ODROID-X board device tree source
- *
- * Copyright (c) 2012 Dongjin Kim
- *
- * Device tree source file for Hardkernel's ODROID-X board which is based on
- * Samsung's Exynos4412 SoC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/dts-v1/;
-/include/ "exynos4412.dtsi"
-
-/ {
- model = "Hardkernel ODROID-X board based on Exynos4412";
- compatible = "hardkernel,odroid-x", "samsung,exynos4412";
-
- memory {
- reg = <0x40000000 0x40000000>;
- };
-
- leds {
- compatible = "gpio-leds";
- led1 {
- label = "led1:heart";
- gpios = <&gpc1 0 1>;
- default-state = "on";
- linux,default-trigger = "heartbeat";
- };
- led2 {
- label = "led2:mmc0";
- gpios = <&gpc1 2 1>;
- default-state = "on";
- linux,default-trigger = "mmc0";
- };
- };
-
- mshc@12550000 {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
- pinctrl-names = "default";
- status = "okay";
-
- num-slots = <1>;
- supports-highspeed;
- broken-cd;
- fifo-depth = <0x80>;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
- };
-
- regulator_p3v3 {
- compatible = "regulator-fixed";
- regulator-name = "p3v3_en";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpa1 1 1>;
- enable-active-high;
- regulator-boot-on;
- };
-
- rtc@10070000 {
- status = "okay";
- };
-
- sdhci@12530000 {
- bus-width = <4>;
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus4>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- serial@13800000 {
- status = "okay";
- };
-
- serial@13810000 {
- status = "okay";
- };
-
- serial@13820000 {
- status = "okay";
- };
-
- serial@13830000 {
- status = "okay";
- };
-
- fixed-rate-clocks {
- xxti {
- compatible = "samsung,clock-xxti";
- clock-frequency = <0>;
- };
-
- xusbxti {
- compatible = "samsung,clock-xusbxti";
- clock-frequency = <24000000>;
- };
- };
-};
diff --git a/trunk/arch/arm/boot/dts/exynos4412-origen.dts b/trunk/arch/arm/boot/dts/exynos4412-origen.dts
deleted file mode 100644
index 1fecf7666dc0..000000000000
--- a/trunk/arch/arm/boot/dts/exynos4412-origen.dts
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * Insignal's Exynos4412 based Origen board device tree source
- *
- * Copyright (c) 2012-2013 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * Device tree source file for Insignal's Origen board which is based on
- * Samsung's Exynos4412 SoC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/dts-v1/;
-/include/ "exynos4412.dtsi"
-
-/ {
- model = "Insignal Origen evaluation board based on Exynos4412";
- compatible = "insignal,origen4412", "samsung,exynos4412";
-
- memory {
- reg = <0x40000000 0x40000000>;
- };
-
- chosen {
- bootargs ="console=ttySAC2,115200";
- };
-
- mmc_reg: voltage-regulator {
- compatible = "regulator-fixed";
- regulator-name = "VMEM_VDD_2.8V";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- gpio = <&gpx1 1 0>;
- enable-active-high;
- };
-
- sdhci@12530000 {
- bus-width = <4>;
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
- pinctrl-names = "default";
- vmmc-supply = <&mmc_reg>;
- status = "okay";
- };
-
- mshc@12550000 {
- #address-cells = <1>;
- #size-cells = <0>;
- pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>;
- pinctrl-names = "default";
- status = "okay";
-
- num-slots = <1>;
- supports-highspeed;
- broken-cd;
- fifo-depth = <0x80>;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- };
- };
-
- codec@13400000 {
- samsung,mfc-r = <0x43000000 0x800000>;
- samsung,mfc-l = <0x51000000 0x800000>;
- status = "okay";
- };
-
- serial@13800000 {
- status = "okay";
- };
-
- serial@13810000 {
- status = "okay";
- };
-
- serial@13820000 {
- status = "okay";
- };
-
- serial@13830000 {
- status = "okay";
- };
-
- i2c@13860000 {
- #address-cells = <1>;
- #size-cells = <0>;
- samsung,i2c-sda-delay = <100>;
- samsung,i2c-max-bus-freq = <20000>;
- pinctrl-0 = <&i2c0_bus>;
- pinctrl-names = "default";
- status = "okay";
-
- s5m8767_pmic@66 {
- compatible = "samsung,s5m8767-pmic";
- reg = <0x66>;
-
- s5m8767,pmic-buck-default-dvs-idx = <3>;
-
- s5m8767,pmic-buck-dvs-gpios = <&gpx2 3 0>,
- <&gpx2 4 0>,
- <&gpx2 5 0>;
-
- s5m8767,pmic-buck-ds-gpios = <&gpm3 5 0>,
- <&gpm3 6 0>,
- <&gpm3 7 0>;
-
- s5m8767,pmic-buck2-dvs-voltage = <1250000>, <1200000>,
- <1200000>, <1200000>,
- <1200000>, <1200000>,
- <1200000>, <1200000>;
-
- s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
- <1100000>, <1100000>,
- <1100000>, <1100000>,
- <1100000>, <1100000>;
-
- s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
- <1200000>, <1200000>,
- <1200000>, <1200000>,
- <1200000>, <1200000>;
-
- regulators {
- ldo1_reg: LDO1 {
- regulator-name = "VDD_ALIVE";
- regulator-min-microvolt = <1100000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- regulator-boot-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo2_reg: LDO2 {
- regulator-name = "VDDQ_M12";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo3_reg: LDO3 {
- regulator-name = "VDDIOAP_18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo4_reg: LDO4 {
- regulator-name = "VDDQ_PRE";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo5_reg: LDO5 {
- regulator-name = "VDD18_2M";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo6_reg: LDO6 {
- regulator-name = "VDD10_MPLL";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo7_reg: LDO7 {
- regulator-name = "VDD10_XPLL";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo8_reg: LDO8 {
- regulator-name = "VDD10_MIPI";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo9_reg: LDO9 {
- regulator-name = "VDD33_LCD";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo10_reg: LDO10 {
- regulator-name = "VDD18_MIPI";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo11_reg: LDO11 {
- regulator-name = "VDD18_ABB1";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo12_reg: LDO12 {
- regulator-name = "VDD33_UOTG";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo13_reg: LDO13 {
- regulator-name = "VDDIOPERI_18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo14_reg: LDO14 {
- regulator-name = "VDD18_ABB02";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo15_reg: LDO15 {
- regulator-name = "VDD10_USH";
- regulator-min-microvolt = <1000000>;
- regulator-max-microvolt = <1000000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo16_reg: LDO16 {
- regulator-name = "VDD18_HSIC";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo17_reg: LDO17 {
- regulator-name = "VDDIOAP_MMC012_28";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo18_reg: LDO18 {
- regulator-name = "VDDIOPERI_28";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo19_reg: LDO19 {
- regulator-name = "DVDD25";
- regulator-min-microvolt = <2500000>;
- regulator-max-microvolt = <2500000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo20_reg: LDO20 {
- regulator-name = "VDD28_CAM";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo21_reg: LDO21 {
- regulator-name = "VDD28_AF";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo22_reg: LDO22 {
- regulator-name = "VDDA28_2M";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo23_reg: LDO23 {
- regulator-name = "VDD28_TF";
- regulator-min-microvolt = <2800000>;
- regulator-max-microvolt = <2800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo24_reg: LDO24 {
- regulator-name = "VDD33_A31";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo25_reg: LDO25 {
- regulator-name = "VDD18_CAM";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo26_reg: LDO26 {
- regulator-name = "VDD18_A31";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo27_reg: LDO27 {
- regulator-name = "GPS_1V8";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- ldo28_reg: LDO28 {
- regulator-name = "DVDD12";
- regulator-min-microvolt = <1200000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- buck1_reg: BUCK1 {
- regulator-name = "vdd_mif";
- regulator-min-microvolt = <950000>;
- regulator-max-microvolt = <1100000>;
- regulator-always-on;
- regulator-boot-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- buck2_reg: BUCK2 {
- regulator-name = "vdd_arm";
- regulator-min-microvolt = <925000>;
- regulator-max-microvolt = <1300000>;
- regulator-always-on;
- regulator-boot-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- buck3_reg: BUCK3 {
- regulator-name = "vdd_int";
- regulator-min-microvolt = <900000>;
- regulator-max-microvolt = <1200000>;
- regulator-always-on;
- regulator-boot-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- buck4_reg: BUCK4 {
- regulator-name = "vdd_g3d";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- buck5_reg: BUCK5 {
- regulator-name = "vdd_m12";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- buck6_reg: BUCK6 {
- regulator-name = "vdd12_5m";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <1500000>;
- regulator-always-on;
- regulator-boot-on;
- op_mode = <1>; /* Normal Mode */
- };
-
- buck9_reg: BUCK9 {
- regulator-name = "vddf28_emmc";
- regulator-min-microvolt = <750000>;
- regulator-max-microvolt = <3000000>;
- regulator-always-on;
- regulator-boot-on;
- op_mode = <1>; /* Normal Mode */
- };
- };
- };
- };
-
- fixed-rate-clocks {
- xxti {
- compatible = "samsung,clock-xxti";
- clock-frequency = <0>;
- };
-
- xusbxti {
- compatible = "samsung,clock-xusbxti";
- clock-frequency = <24000000>;
- };
- };
-};
diff --git a/trunk/arch/arm/boot/dts/exynos4412-smdk4412.dts b/trunk/arch/arm/boot/dts/exynos4412-smdk4412.dts
index 874beeaef99d..f05bf575cc45 100644
--- a/trunk/arch/arm/boot/dts/exynos4412-smdk4412.dts
+++ b/trunk/arch/arm/boot/dts/exynos4412-smdk4412.dts
@@ -27,19 +27,6 @@
bootargs ="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc";
};
- sdhci@12530000 {
- bus-width = <4>;
- pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sd2_cd>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- codec@13400000 {
- samsung,mfc-r = <0x43000000 0x800000>;
- samsung,mfc-l = <0x51000000 0x800000>;
- status = "okay";
- };
-
serial@13800000 {
status = "okay";
};
@@ -55,16 +42,4 @@
serial@13830000 {
status = "okay";
};
-
- fixed-rate-clocks {
- xxti {
- compatible = "samsung,clock-xxti";
- clock-frequency = <0>;
- };
-
- xusbxti {
- compatible = "samsung,clock-xusbxti";
- clock-frequency = <24000000>;
- };
- };
};
diff --git a/trunk/arch/arm/boot/dts/exynos4412.dtsi b/trunk/arch/arm/boot/dts/exynos4412.dtsi
index d75c047e80a9..d7dfe312772a 100644
--- a/trunk/arch/arm/boot/dts/exynos4412.dtsi
+++ b/trunk/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,30 +25,4 @@
gic:interrupt-controller@10490000 {
cpu-offset = <0x4000>;
};
-
- mct@10050000 {
- compatible = "samsung,exynos4412-mct";
- reg = <0x10050000 0x800>;
- interrupt-controller;
- #interrups-cells = <2>;
- interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
- <4 0>, <5 0>, <6 0>, <7 0>;
- clocks = <&clock 3>, <&clock 344>;
- clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <2>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0x0 0 &gic 0 57 0>,
- <0x1 0 &combiner 12 5>,
- <0x2 0 &combiner 12 6>,
- <0x3 0 &combiner 12 7>,
- <0x4 0 &gic 1 12 0>,
- <0x5 0 &gic 1 12 0>,
- <0x6 0 &gic 1 12 0>,
- <0x7 0 &gic 1 12 0>;
- };
- };
};
diff --git a/trunk/arch/arm/boot/dts/exynos4x12.dtsi b/trunk/arch/arm/boot/dts/exynos4x12.dtsi
index 7496b8d633ea..9a8780694909 100644
--- a/trunk/arch/arm/boot/dts/exynos4x12.dtsi
+++ b/trunk/arch/arm/boot/dts/exynos4x12.dtsi
@@ -36,12 +36,6 @@
<0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>;
};
- clock: clock-controller@0x10030000 {
- compatible = "samsung,exynos4412-clock";
- reg = <0x10030000 0x20000>;
- #clock-cells = <1>;
- };
-
pinctrl_0: pinctrl@11400000 {
compatible = "samsung,exynos4x12-pinctrl";
reg = <0x11400000 0x1000>;
diff --git a/trunk/arch/arm/boot/dts/exynos5250-arndale.dts b/trunk/arch/arm/boot/dts/exynos5250-arndale.dts
deleted file mode 100644
index 5de019cb0e58..000000000000
--- a/trunk/arch/arm/boot/dts/exynos5250-arndale.dts
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * Samsung's Exynos5250 based Arndale board device tree source
- *
- * Copyright (c) 2013 Samsung Electronics Co., Ltd.
- * http://www.samsung.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/dts-v1/;
-/include/ "exynos5250.dtsi"
-
-/ {
- model = "Insignal Arndale evaluation board based on EXYNOS5250";
- compatible = "insignal,arndale", "samsung,exynos5250";
-
- memory {
- reg = <0x40000000 0x80000000>;
- };
-
- chosen {
- bootargs = "console=ttySAC2,115200";
- };
-
- i2c@12C60000 {
- status = "disabled";
- };
-
- i2c@12C70000 {
- status = "disabled";
- };
-
- i2c@12C80000 {
- status = "disabled";
- };
-
- i2c@12C90000 {
- status = "disabled";
- };
-
- i2c@12CA0000 {
- status = "disabled";
- };
-
- i2c@12CB0000 {
- status = "disabled";
- };
-
- i2c@12CC0000 {
- status = "disabled";
- };
-
- i2c@12CD0000 {
- status = "disabled";
- };
-
- i2c@121D0000 {
- status = "disabled";
- };
-
- dwmmc_0: dwmmc0@12200000 {
- num-slots = <1>;
- supports-highspeed;
- broken-cd;
- fifo-depth = <0x80>;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
-
- slot@0 {
- reg = <0>;
- bus-width = <8>;
- gpios = <&gpc0 0 2 0 3>, <&gpc0 1 2 0 3>,
- <&gpc0 3 2 3 3>, <&gpc0 4 2 3 3>,
- <&gpc0 5 2 3 3>, <&gpc0 6 2 3 3>,
- <&gpc1 0 2 3 3>, <&gpc1 1 2 3 3>,
- <&gpc1 2 2 3 3>, <&gpc1 3 2 3 3>;
- };
- };
-
- dwmmc_1: dwmmc1@12210000 {
- status = "disabled";
- };
-
- dwmmc_2: dwmmc2@12220000 {
- num-slots = <1>;
- supports-highspeed;
- fifo-depth = <0x80>;
- card-detect-delay = <200>;
- samsung,dw-mshc-ciu-div = <3>;
- samsung,dw-mshc-sdr-timing = <2 3>;
- samsung,dw-mshc-ddr-timing = <1 2>;
-
- slot@0 {
- reg = <0>;
- bus-width = <4>;
- samsung,cd-pinmux-gpio = <&gpc3 2 2 3 3>;
- gpios = <&gpc3 0 2 0 3>, <&gpc3 1 2 0 3>,
- <&gpc3 3 2 3 3>, <&gpc3 4 2 3 3>,
- <&gpc3 5 2 3 3>, <&gpc3 6 2 3 3>;
- };
- };
-
- dwmmc_3: dwmmc3@12230000 {
- status = "disabled";
- };
-
- spi_0: spi@12d20000 {
- status = "disabled";
- };
-
- spi_1: spi@12d30000 {
- status = "disabled";
- };
-
- spi_2: spi@12d40000 {
- status = "disabled";
- };
-
- fixed-rate-clocks {
- xxti {
- compatible = "samsung,clock-xxti";
- clock-frequency = <24000000>;
- };
- };
-};
diff --git a/trunk/arch/arm/boot/dts/exynos5250-smdk5250.dts b/trunk/arch/arm/boot/dts/exynos5250-smdk5250.dts
index 872ae1f93c75..1b8d4106d338 100644
--- a/trunk/arch/arm/boot/dts/exynos5250-smdk5250.dts
+++ b/trunk/arch/arm/boot/dts/exynos5250-smdk5250.dts
@@ -231,24 +231,4 @@
samsung,i2s-controller = <&i2s0>;
samsung,audio-codec = <&wm8994>;
};
-
- usb@12110000 {
- samsung,vbus-gpio = <&gpx2 6 1 3 3>;
- };
-
- dp-controller {
- samsung,color-space = <0>;
- samsung,dynamic-range = <0>;
- samsung,ycbcr-coeff = <0>;
- samsung,color-depth = <1>;
- samsung,link-rate = <0x0a>;
- samsung,lane-count = <4>;
- };
-
- fixed-rate-clocks {
- xxti {
- compatible = "samsung,clock-xxti";
- clock-frequency = <24000000>;
- };
- };
};
diff --git a/trunk/arch/arm/boot/dts/exynos5250-snow.dts b/trunk/arch/arm/boot/dts/exynos5250-snow.dts
index babd9f9b1bf9..17dd951c1cd2 100644
--- a/trunk/arch/arm/boot/dts/exynos5250-snow.dts
+++ b/trunk/arch/arm/boot/dts/exynos5250-snow.dts
@@ -40,15 +40,4 @@
<&gpc4 5 2 3 0>, <&gpc4 6 2 3 0>;
};
};
-
- usb@12110000 {
- samsung,vbus-gpio = <&gpx1 1 1 3 3>;
- };
-
- fixed-rate-clocks {
- xxti {
- compatible = "samsung,clock-xxti";
- clock-frequency = <24000000>;
- };
- };
};
diff --git a/trunk/arch/arm/boot/dts/exynos5250.dtsi b/trunk/arch/arm/boot/dts/exynos5250.dtsi
index 28758e5dd15c..b1ac73e21c80 100644
--- a/trunk/arch/arm/boot/dts/exynos5250.dtsi
+++ b/trunk/arch/arm/boot/dts/exynos5250.dtsi
@@ -46,22 +46,6 @@
i2c8 = &i2c_8;
};
- pd_gsc: gsc-power-domain@0x10044000 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10044000 0x20>;
- };
-
- pd_mfc: mfc-power-domain@0x10044040 {
- compatible = "samsung,exynos4210-pd";
- reg = <0x10044040 0x20>;
- };
-
- clock: clock-controller@0x10010000 {
- compatible = "samsung,exynos5250-clock";
- reg = <0x10010000 0x30000>;
- #clock-cells = <1>;
- };
-
gic:interrupt-controller@10481000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
@@ -85,106 +69,58 @@
<0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
};
- mct@101C0000 {
- compatible = "samsung,exynos4210-mct";
- reg = <0x101C0000 0x800>;
- interrupt-controller;
- #interrups-cells = <2>;
- interrupt-parent = <&mct_map>;
- interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
- <4 0>, <5 0>;
- clocks = <&clock 1>, <&clock 335>;
- clock-names = "fin_pll", "mct";
-
- mct_map: mct-map {
- #interrupt-cells = <2>;
- #address-cells = <0>;
- #size-cells = <0>;
- interrupt-map = <0x0 0 &combiner 23 3>,
- <0x1 0 &combiner 23 4>,
- <0x2 0 &combiner 25 2>,
- <0x3 0 &combiner 25 3>,
- <0x4 0 &gic 0 120 0>,
- <0x5 0 &gic 0 121 0>;
- };
- };
-
- pmu {
- compatible = "arm,cortex-a15-pmu";
- interrupt-parent = <&combiner>;
- interrupts = <1 2>, <22 4>;
- };
-
watchdog {
compatible = "samsung,s3c2410-wdt";
reg = <0x101D0000 0x100>;
interrupts = <0 42 0>;
- clocks = <&clock 336>;
- clock-names = "watchdog";
};
codec@11000000 {
compatible = "samsung,mfc-v6";
reg = <0x11000000 0x10000>;
interrupts = <0 96 0>;
- samsung,power-domain = <&pd_mfc>;
};
rtc {
compatible = "samsung,s3c6410-rtc";
reg = <0x101E0000 0x100>;
interrupts = <0 43 0>, <0 44 0>;
- clocks = <&clock 337>;
- clock-names = "rtc";
- status = "disabled";
};
tmu@10060000 {
compatible = "samsung,exynos5250-tmu";
reg = <0x10060000 0x100>;
interrupts = <0 65 0>;
- clocks = <&clock 338>;
- clock-names = "tmu_apbif";
};
serial@12C00000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C00000 0x100>;
interrupts = <0 51 0>;
- clocks = <&clock 289>, <&clock 146>;
- clock-names = "uart", "clk_uart_baud0";
};
serial@12C10000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C10000 0x100>;
interrupts = <0 52 0>;
- clocks = <&clock 290>, <&clock 147>;
- clock-names = "uart", "clk_uart_baud0";
};
serial@12C20000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C20000 0x100>;
interrupts = <0 53 0>;
- clocks = <&clock 291>, <&clock 148>;
- clock-names = "uart", "clk_uart_baud0";
};
serial@12C30000 {
compatible = "samsung,exynos4210-uart";
reg = <0x12C30000 0x100>;
interrupts = <0 54 0>;
- clocks = <&clock 292>, <&clock 149>;
- clock-names = "uart", "clk_uart_baud0";
};
sata@122F0000 {
compatible = "samsung,exynos5-sata-ahci";
reg = <0x122F0000 0x1ff>;
interrupts = <0 115 0>;
- clocks = <&clock 277>, <&clock 143>;
- clock-names = "sata", "sclk_sata";
};
sata-phy@12170000 {
@@ -198,8 +134,6 @@
interrupts = <0 56 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 294>;
- clock-names = "i2c";
};
i2c_1: i2c@12C70000 {
@@ -208,8 +142,6 @@
interrupts = <0 57 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 295>;
- clock-names = "i2c";
};
i2c_2: i2c@12C80000 {
@@ -218,8 +150,6 @@
interrupts = <0 58 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 296>;
- clock-names = "i2c";
};
i2c_3: i2c@12C90000 {
@@ -228,8 +158,6 @@
interrupts = <0 59 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 297>;
- clock-names = "i2c";
};
i2c_4: i2c@12CA0000 {
@@ -238,8 +166,6 @@
interrupts = <0 60 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 298>;
- clock-names = "i2c";
};
i2c_5: i2c@12CB0000 {
@@ -248,8 +174,6 @@
interrupts = <0 61 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 299>;
- clock-names = "i2c";
};
i2c_6: i2c@12CC0000 {
@@ -258,8 +182,6 @@
interrupts = <0 62 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 300>;
- clock-names = "i2c";
};
i2c_7: i2c@12CD0000 {
@@ -268,8 +190,6 @@
interrupts = <0 63 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 301>;
- clock-names = "i2c";
};
i2c_8: i2c@12CE0000 {
@@ -278,8 +198,6 @@
interrupts = <0 64 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 302>;
- clock-names = "i2c";
};
i2c@121D0000 {
@@ -287,8 +205,6 @@
reg = <0x121D0000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 288>;
- clock-names = "i2c";
};
spi_0: spi@12d20000 {
@@ -300,8 +216,6 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 304>, <&clock 154>;
- clock-names = "spi", "spi_busclk0";
};
spi_1: spi@12d30000 {
@@ -313,8 +227,6 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 305>, <&clock 155>;
- clock-names = "spi", "spi_busclk0";
};
spi_2: spi@12d40000 {
@@ -326,8 +238,6 @@
dma-names = "tx", "rx";
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 306>, <&clock 156>;
- clock-names = "spi", "spi_busclk0";
};
dwmmc_0: dwmmc0@12200000 {
@@ -336,8 +246,6 @@
interrupts = <0 75 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 280>, <&clock 139>;
- clock-names = "biu", "ciu";
};
dwmmc_1: dwmmc1@12210000 {
@@ -346,8 +254,6 @@
interrupts = <0 76 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 281>, <&clock 140>;
- clock-names = "biu", "ciu";
};
dwmmc_2: dwmmc2@12220000 {
@@ -356,8 +262,6 @@
interrupts = <0 77 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 282>, <&clock 141>;
- clock-names = "biu", "ciu";
};
dwmmc_3: dwmmc3@12230000 {
@@ -366,8 +270,6 @@
interrupts = <0 78 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 283>, <&clock 142>;
- clock-names = "biu", "ciu";
};
i2s0: i2s@03830000 {
@@ -399,18 +301,6 @@
dma-names = "tx", "rx";
};
- usb@12110000 {
- compatible = "samsung,exynos4210-ehci";
- reg = <0x12110000 0x100>;
- interrupts = <0 71 0>;
- };
-
- usb@12120000 {
- compatible = "samsung,exynos4210-ohci";
- reg = <0x12120000 0x100>;
- interrupts = <0 71 0>;
- };
-
amba {
#address-cells = <1>;
#size-cells = <1>;
@@ -422,8 +312,6 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x121A0000 0x1000>;
interrupts = <0 34 0>;
- clocks = <&clock 275>;
- clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
@@ -433,8 +321,6 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x121B0000 0x1000>;
interrupts = <0 35 0>;
- clocks = <&clock 276>;
- clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
@@ -444,8 +330,6 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>;
interrupts = <0 33 0>;
- clocks = <&clock 271>;
- clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
@@ -455,8 +339,6 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x11C10000 0x1000>;
interrupts = <0 124 0>;
- clocks = <&clock 271>;
- clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <1>;
@@ -710,51 +592,34 @@
};
};
-
gsc_0: gsc@0x13e00000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e00000 0x1000>;
interrupts = <0 85 0>;
- samsung,power-domain = <&pd_gsc>;
- clocks = <&clock 256>;
- clock-names = "gscl";
};
gsc_1: gsc@0x13e10000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e10000 0x1000>;
interrupts = <0 86 0>;
- samsung,power-domain = <&pd_gsc>;
- clocks = <&clock 257>;
- clock-names = "gscl";
};
gsc_2: gsc@0x13e20000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e20000 0x1000>;
interrupts = <0 87 0>;
- samsung,power-domain = <&pd_gsc>;
- clocks = <&clock 258>;
- clock-names = "gscl";
};
gsc_3: gsc@0x13e30000 {
compatible = "samsung,exynos5-gsc";
reg = <0x13e30000 0x1000>;
interrupts = <0 88 0>;
- samsung,power-domain = <&pd_gsc>;
- clocks = <&clock 259>;
- clock-names = "gscl";
};
hdmi {
compatible = "samsung,exynos5-hdmi";
reg = <0x14530000 0x70000>;
interrupts = <0 95 0>;
- clocks = <&clock 333>, <&clock 136>, <&clock 137>,
- <&clock 333>, <&clock 333>;
- clock-names = "hdmi", "sclk_hdmi", "sclk_pixel",
- "sclk_hdmiphy", "hdmiphy";
};
mixer {
@@ -762,18 +627,4 @@
reg = <0x14450000 0x10000>;
interrupts = <0 94 0>;
};
-
- dp-controller {
- compatible = "samsung,exynos5-dp";
- reg = <0x145b0000 0x1000>;
- interrupts = <10 3>;
- interrupt-parent = <&combiner>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- dptx-phy {
- reg = <0x10040720>;
- samsung,enable-mask = <1>;
- };
- };
};
diff --git a/trunk/arch/arm/boot/dts/exynos5440-ssdk5440.dts b/trunk/arch/arm/boot/dts/exynos5440-ssdk5440.dts
index a21eb4cbe893..81e2c964a900 100644
--- a/trunk/arch/arm/boot/dts/exynos5440-ssdk5440.dts
+++ b/trunk/arch/arm/boot/dts/exynos5440-ssdk5440.dts
@@ -28,10 +28,19 @@
status = "disabled";
};
- fixed-rate-clocks {
- xtal {
- compatible = "samsung,clock-xtal";
- clock-frequency = <50000000>;
- };
+ i2c@F0000 {
+ status = "disabled";
+ };
+
+ i2c@100000 {
+ status = "disabled";
+ };
+
+ watchdog {
+ status = "disabled";
+ };
+
+ rtc {
+ status = "disabled";
};
};
diff --git a/trunk/arch/arm/boot/dts/exynos5440.dtsi b/trunk/arch/arm/boot/dts/exynos5440.dtsi
index 48cc96aa0b5f..9a99755920c0 100644
--- a/trunk/arch/arm/boot/dts/exynos5440.dtsi
+++ b/trunk/arch/arm/boot/dts/exynos5440.dtsi
@@ -16,12 +16,6 @@
interrupt-parent = <&gic>;
- clock: clock-controller@0x160000 {
- compatible = "samsung,exynos5440-clock";
- reg = <0x160000 0x1000>;
- #clock-cells = <1>;
- };
-
gic:interrupt-controller@2E0000 {
compatible = "arm,cortex-a15-gic";
#interrupt-cells = <3>;
@@ -30,51 +24,55 @@
};
cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
cpu@0 {
compatible = "arm,cortex-a15";
- reg = <0>;
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 13 0xf08>;
+ clock-frequency = <1000000>;
+ };
};
cpu@1 {
compatible = "arm,cortex-a15";
- reg = <1>;
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 14 0xf08>;
+ clock-frequency = <1000000>;
+ };
};
cpu@2 {
compatible = "arm,cortex-a15";
- reg = <2>;
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 14 0xf08>;
+ clock-frequency = <1000000>;
+ };
};
cpu@3 {
compatible = "arm,cortex-a15";
- reg = <3>;
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <1 14 0xf08>;
+ clock-frequency = <1000000>;
+ };
};
};
- timer {
- compatible = "arm,cortex-a15-timer",
- "arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
- clock-frequency = <50000000>;
+ common {
+ compatible = "samsung,exynos5440";
+
};
serial@B0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xB0000 0x1000>;
interrupts = <0 2 0>;
- clocks = <&clock 21>, <&clock 21>;
- clock-names = "uart", "clk_uart_baud0";
};
serial@C0000 {
compatible = "samsung,exynos4210-uart";
reg = <0xC0000 0x1000>;
interrupts = <0 3 0>;
- clocks = <&clock 21>, <&clock 21>;
- clock-names = "uart", "clk_uart_baud0";
};
spi {
@@ -85,8 +83,6 @@
rx-dma-channel = <&pdma0 4>; /* preliminary */
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 21>, <&clock 16>;
- clock-names = "spi", "spi_busclk0";
};
pinctrl {
@@ -114,31 +110,25 @@
};
i2c@F0000 {
- compatible = "samsung,exynos5440-i2c";
+ compatible = "samsung,s3c2440-i2c";
reg = <0xF0000 0x1000>;
interrupts = <0 5 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 21>;
- clock-names = "i2c";
};
i2c@100000 {
- compatible = "samsung,exynos5440-i2c";
+ compatible = "samsung,s3c2440-i2c";
reg = <0x100000 0x1000>;
interrupts = <0 6 0>;
#address-cells = <1>;
#size-cells = <0>;
- clocks = <&clock 21>;
- clock-names = "i2c";
};
watchdog {
compatible = "samsung,s3c2410-wdt";
reg = <0x110000 0x1000>;
interrupts = <0 1 0>;
- clocks = <&clock 21>;
- clock-names = "watchdog";
};
amba {
@@ -152,8 +142,6 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x120000 0x1000>;
interrupts = <0 34 0>;
- clocks = <&clock 21>;
- clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
@@ -163,8 +151,6 @@
compatible = "arm,pl330", "arm,primecell";
reg = <0x121000 0x1000>;
interrupts = <0 35 0>;
- clocks = <&clock 21>;
- clock-names = "apb_pclk";
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <32>;
@@ -175,8 +161,5 @@
compatible = "samsung,s3c6410-rtc";
reg = <0x130000 0x1000>;
interrupts = <0 17 0>, <0 16 0>;
- clocks = <&clock 21>;
- clock-names = "rtc";
- status = "disabled";
};
};
diff --git a/trunk/arch/arm/boot/dts/kirkwood-cloudbox.dts b/trunk/arch/arm/boot/dts/kirkwood-cloudbox.dts
deleted file mode 100644
index 5f21d4e427b0..000000000000
--- a/trunk/arch/arm/boot/dts/kirkwood-cloudbox.dts
+++ /dev/null
@@ -1,89 +0,0 @@
-/dts-v1/;
-
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6281.dtsi"
-
-/ {
- model = "LaCie CloudBox";
- compatible = "lacie,cloudbox", "marvell,kirkwood-88f6702", "marvell,kirkwood";
-
- memory {
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8";
- };
-
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
- pinctrl-0 = < &pmx_spi &pmx_uart0
- &pmx_cloudbox_sata0 >;
- pinctrl-names = "default";
-
- pmx_cloudbox_sata0: pmx-cloudbox-sata0 {
- marvell,pins = "mpp15";
- marvell,function = "sata0";
- };
- };
-
- serial@12000 {
- clock-frequency = <166666667>;
- status = "okay";
- };
-
- sata@80000 {
- status = "okay";
- nr-ports = <1>;
- };
-
- spi@10600 {
- status = "okay";
-
- flash@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "mx25l4005a";
- reg = <0>;
- spi-max-frequency = <20000000>;
- mode = <0>;
-
- partition@0 {
- reg = <0x0 0x80000>;
- label = "u-boot";
- };
- };
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
-
- button@1 {
- label = "Power push button";
- linux,code = <116>;
- gpios = <&gpio0 16 1>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- red-fail {
- label = "cloudbox:red:fail";
- gpios = <&gpio0 14 0>;
- };
- blue-sata {
- label = "cloudbox:blue:sata";
- gpios = <&gpio0 15 0>;
- };
- };
-
- gpio_poweroff {
- compatible = "gpio-poweroff";
- gpios = <&gpio0 17 0>;
- };
-};
diff --git a/trunk/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts b/trunk/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
deleted file mode 100644
index 1ca66ab83ad6..000000000000
--- a/trunk/arch/arm/boot/dts/kirkwood-netgear_readynas_duo_v2.dts
+++ /dev/null
@@ -1,180 +0,0 @@
-/dts-v1/;
-
-/include/ "kirkwood.dtsi"
-/include/ "kirkwood-6282.dtsi"
-
-/ {
- model = "NETGEAR ReadyNAS Duo v2";
- compatible = "netgear,readynas-duo-v2", "netgear,readynas", "marvell,kirkwood-88f6282", "marvell,kirkwood";
-
- memory { /* 256 MB */
- device_type = "memory";
- reg = <0x00000000 0x10000000>;
- };
-
- chosen {
- bootargs = "console=ttyS0,115200n8 earlyprintk";
- };
-
- ocp@f1000000 {
- pinctrl: pinctrl@10000 {
-
- pinctrl-0 = < &pmx_uart0
- &pmx_button_power
- &pmx_button_backup
- &pmx_button_reset
- &pmx_led_blue_power
- &pmx_led_blue_activity
- &pmx_led_blue_disk1
- &pmx_led_blue_disk2
- &pmx_led_blue_backup >;
- pinctrl-names = "default";
-
- pmx_button_power: pmx-button-power {
- marvell,pins = "mpp47";
- marvell,function = "gpio";
- };
- pmx_button_backup: pmx-button-backup {
- marvell,pins = "mpp45";
- marvell,function = "gpio";
- };
- pmx_button_reset: pmx-button-reset {
- marvell,pins = "mpp13";
- marvell,function = "gpio";
- };
- pmx_led_blue_power: pmx-led-blue-power {
- marvell,pins = "mpp31";
- marvell,function = "gpio";
- };
- pmx_led_blue_activity: pmx-led-blue-activity {
- marvell,pins = "mpp38";
- marvell,function = "gpio";
- };
- pmx_led_blue_disk1: pmx-led-blue-disk1 {
- marvell,pins = "mpp23";
- marvell,function = "gpio";
- };
- pmx_led_blue_disk2: pmx-led-blue-disk2 {
- marvell,pins = "mpp22";
- marvell,function = "gpio";
- };
- pmx_led_blue_backup: pmx-led-blue-backup {
- marvell,pins = "mpp29";
- marvell,function = "gpio";
- };
- };
-
- i2c@11000 {
- status = "okay";
-
- rs5c372a: rs5c372a@32 {
- compatible = "ricoh,rs5c372a";
- reg = <0x32>;
- };
- };
-
- serial@12000 {
- status = "okay";
- };
-
- nand@3000000 {
- status = "okay";
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x180000>;
- read-only;
- };
-
- partition@180000 {
- label = "u-boot-env";
- reg = <0x180000 0x20000>;
- };
-
- partition@200000 {
- label = "uImage";
- reg = <0x0200000 0x600000>;
- };
-
- partition@800000 {
- label = "minirootfs";
- reg = <0x0800000 0x1000000>;
- };
-
- partition@1800000 {
- label = "jffs2";
- reg = <0x1800000 0x6800000>;
- };
- };
-
- sata@80000 {
- status = "okay";
- nr-ports = <2>;
- };
- };
-
- gpio-leds {
- compatible = "gpio-leds";
-
- power_led {
- label = "status:blue:power_led";
- gpios = <&gpio0 31 1>; /* GPIO 31 Active Low */
- linux,default-trigger = "default-on";
- };
- activity_led {
- label = "status:blue:activity_led";
- gpios = <&gpio1 6 1>; /* GPIO 38 Active Low */
- };
- disk1_led {
- label = "status:blue:disk1_led";
- gpios = <&gpio0 23 1>; /* GPIO 23 Active Low */
- };
- disk2_led {
- label = "status:blue:disk2_led";
- gpios = <&gpio0 22 1>; /* GPIO 22 Active Low */
- };
- backup_led {
- label = "status:blue:backup_led";
- gpios = <&gpio0 29 1>; /* GPIO 29 Active Low*/
- };
- };
-
- gpio_keys {
- compatible = "gpio-keys";
- #address-cells = <1>;
- #size-cells = <0>;
- button@1 {
- label = "Power Button";
- linux,code = <116>; /* KEY_POWER */
- gpios = <&gpio1 15 1>;
- };
- button@2 {
- label = "Reset Button";
- linux,code = <0x198>; /* KEY_RESTART */
- gpios = <&gpio0 13 1>;
- };
- button@3 {
- label = "Backup Button";
- linux,code = <133>; /* KEY_COPY */
- gpios = <&gpio1 13 1>;
- };
- };
-
- regulators {
- compatible = "simple-bus";
- #address-cells = <1>;
- #size-cells = <0>;
-
- usb_power: regulator@1 {
- compatible = "regulator-fixed";
- reg = <1>;
- regulator-name = "USB 3.0 Power";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- enable-active-high;
- regulator-always-on;
- regulator-boot-on;
- gpio = <&gpio1 14 0>;
- };
- };
-};
diff --git a/trunk/arch/arm/boot/dts/kirkwood-ns2mini.dts b/trunk/arch/arm/boot/dts/kirkwood-ns2mini.dts
index adab1ab25733..b79f5eb25589 100644
--- a/trunk/arch/arm/boot/dts/kirkwood-ns2mini.dts
+++ b/trunk/arch/arm/boot/dts/kirkwood-ns2mini.dts
@@ -3,7 +3,6 @@
/include/ "kirkwood-ns2-common.dtsi"
/ {
- /* This machine is embedded in the first LaCie CloudBox product. */
model = "LaCie Network Space Mini v2";
compatible = "lacie,netspace_mini_v2", "marvell,kirkwood-88f6192", "marvell,kirkwood";
diff --git a/trunk/arch/arm/boot/dts/mmp2.dtsi b/trunk/arch/arm/boot/dts/mmp2.dtsi
index 4e8b08c628c7..1429ac05b36d 100644
--- a/trunk/arch/arm/boot/dts/mmp2.dtsi
+++ b/trunk/arch/arm/boot/dts/mmp2.dtsi
@@ -160,7 +160,7 @@
};
gpio@d4019000 {
- compatible = "marvell,mmp2-gpio";
+ compatible = "mrvl,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
diff --git a/trunk/arch/arm/boot/dts/omap3-beagle.dts b/trunk/arch/arm/boot/dts/omap3-beagle.dts
index 02d23f15fd86..f624dc85d441 100644
--- a/trunk/arch/arm/boot/dts/omap3-beagle.dts
+++ b/trunk/arch/arm/boot/dts/omap3-beagle.dts
@@ -38,57 +38,6 @@
};
};
- /* HS USB Port 2 RESET */
- hsusb2_reset: hsusb2_reset_reg {
- compatible = "regulator-fixed";
- regulator-name = "hsusb2_reset";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&gpio5 19 0>; /* gpio_147 */
- startup-delay-us = <70000>;
- enable-active-high;
- };
-
- /* HS USB Port 2 Power */
- hsusb2_power: hsusb2_power_reg {
- compatible = "regulator-fixed";
- regulator-name = "hsusb2_vbus";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
- startup-delay-us = <70000>;
- };
-
- /* HS USB Host PHY on PORT 2 */
- hsusb2_phy: hsusb2_phy {
- compatible = "usb-nop-xceiv";
- reset-supply = <&hsusb2_reset>;
- vcc-supply = <&hsusb2_power>;
- };
-};
-
-&omap3_pmx_core {
- pinctrl-names = "default";
- pinctrl-0 = <
- &hsusbb2_pins
- >;
-
- hsusbb2_pins: pinmux_hsusbb2_pins {
- pinctrl-single,pins = <
- 0x5c0 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_clk OUTPUT */
- 0x5c2 0x3 /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_stp OUTPUT */
- 0x5c4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dir INPUT | PULLDOWN */
- 0x5c6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_nxt INPUT | PULLDOWN */
- 0x5c8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat0 INPUT | PULLDOWN */
- 0x5cA 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat1 INPUT | PULLDOWN */
- 0x1a4 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat2 INPUT | PULLDOWN */
- 0x1a6 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat3 INPUT | PULLDOWN */
- 0x1a8 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat4 INPUT | PULLDOWN */
- 0x1aa 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat5 INPUT | PULLDOWN */
- 0x1ac 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat6 INPUT | PULLDOWN */
- 0x1ae 0x10b /* USBB2_ULPITLL_CLK_MUXMODE.usbb1_ulpiphy_dat7 INPUT | PULLDOWN */
- >;
- };
};
&i2c1 {
@@ -116,23 +65,3 @@
&mmc3 {
status = "disabled";
};
-
-&usbhshost {
- port2-mode = "ehci-phy";
-};
-
-&usbhsehci {
- phys = <0 &hsusb2_phy>;
-};
-
-&twl_gpio {
- ti,use-leds;
- /* pullups: BIT(1) */
- ti,pullups = <0x000002>;
- /*
- * pulldowns:
- * BIT(2), BIT(6), BIT(7), BIT(8), BIT(13)
- * BIT(15), BIT(16), BIT(17)
- */
- ti,pulldowns = <0x03a1c4>;
-};
diff --git a/trunk/arch/arm/boot/dts/omap3.dtsi b/trunk/arch/arm/boot/dts/omap3.dtsi
index a14f74bbce7c..1acc26148ffc 100644
--- a/trunk/arch/arm/boot/dts/omap3.dtsi
+++ b/trunk/arch/arm/boot/dts/omap3.dtsi
@@ -397,36 +397,5 @@
ti,timer-alwon;
ti,timer-secure;
};
-
- usbhstll: usbhstll@48062000 {
- compatible = "ti,usbhs-tll";
- reg = <0x48062000 0x1000>;
- interrupts = <78>;
- ti,hwmods = "usb_tll_hs";
- };
-
- usbhshost: usbhshost@48064000 {
- compatible = "ti,usbhs-host";
- reg = <0x48064000 0x400>;
- ti,hwmods = "usb_host_hs";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usbhsohci: ohci@48064400 {
- compatible = "ti,ohci-omap3", "usb-ohci";
- reg = <0x48064400 0x400>;
- interrupt-parent = <&intc>;
- interrupts = <76>;
- };
-
- usbhsehci: ehci@48064800 {
- compatible = "ti,ehci-omap", "usb-ehci";
- reg = <0x48064800 0x400>;
- interrupt-parent = <&intc>;
- interrupts = <77>;
- };
- };
-
};
};
diff --git a/trunk/arch/arm/boot/dts/omap4.dtsi b/trunk/arch/arm/boot/dts/omap4.dtsi
index b7db1a2b6ca7..739bb79e410e 100644
--- a/trunk/arch/arm/boot/dts/omap4.dtsi
+++ b/trunk/arch/arm/boot/dts/omap4.dtsi
@@ -529,35 +529,5 @@
ti,hwmods = "timer11";
ti,timer-pwm;
};
-
- usbhstll: usbhstll@4a062000 {
- compatible = "ti,usbhs-tll";
- reg = <0x4a062000 0x1000>;
- interrupts = <0 78 0x4>;
- ti,hwmods = "usb_tll_hs";
- };
-
- usbhshost: usbhshost@4a064000 {
- compatible = "ti,usbhs-host";
- reg = <0x4a064000 0x800>;
- ti,hwmods = "usb_host_hs";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- usbhsohci: ohci@4a064800 {
- compatible = "ti,ohci-omap3", "usb-ohci";
- reg = <0x4a064800 0x400>;
- interrupt-parent = <&gic>;
- interrupts = <0 76 0x4>;
- };
-
- usbhsehci: ehci@4a064c00 {
- compatible = "ti,ehci-omap", "usb-ehci";
- reg = <0x4a064c00 0x400>;
- interrupt-parent = <&gic>;
- interrupts = <0 77 0x4>;
- };
- };
};
};
diff --git a/trunk/arch/arm/boot/dts/pxa168.dtsi b/trunk/arch/arm/boot/dts/pxa168.dtsi
index 975dad21ac38..31a718696080 100644
--- a/trunk/arch/arm/boot/dts/pxa168.dtsi
+++ b/trunk/arch/arm/boot/dts/pxa168.dtsi
@@ -77,7 +77,7 @@
};
gpio@d4019000 {
- compatible = "marvell,mmp-gpio";
+ compatible = "mrvl,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
diff --git a/trunk/arch/arm/boot/dts/pxa910.dtsi b/trunk/arch/arm/boot/dts/pxa910.dtsi
index 0247c622f580..825aaca33034 100644
--- a/trunk/arch/arm/boot/dts/pxa910.dtsi
+++ b/trunk/arch/arm/boot/dts/pxa910.dtsi
@@ -89,7 +89,7 @@
};
gpio@d4019000 {
- compatible = "marvell,mmp-gpio";
+ compatible = "mrvl,mmp-gpio";
#address-cells = <1>;
#size-cells = <1>;
reg = <0xd4019000 0x1000>;
diff --git a/trunk/arch/arm/boot/dts/r8a7779-marzen-reference.dts b/trunk/arch/arm/boot/dts/r8a7779-marzen-reference.dts
deleted file mode 100644
index 72be4c87cfb5..000000000000
--- a/trunk/arch/arm/boot/dts/r8a7779-marzen-reference.dts
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Reference Device Tree Source for the Marzen board
- *
- * Copyright (C) 2013 Renesas Solutions Corp.
- * Copyright (C) 2013 Simon Horman
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-/include/ "r8a7779.dtsi"
-
-/ {
- model = "marzen";
- compatible = "renesas,marzen-reference", "renesas,r8a7779";
-
- chosen {
- bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
- };
-
- memory {
- device_type = "memory";
- reg = <0x60000000 0x40000000>;
- };
-
- fixedregulator3v3: fixedregulator@0 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- lan0@18000000 {
- compatible = "smsc,lan9220", "smsc,lan9115";
- reg = <0x18000000 0x100>;
- phy-mode = "mii";
- interrupt-parent = <&gic>;
- interrupts = <0 28 0x4>;
- reg-io-width = <4>;
- vddvario-supply = <&fixedregulator3v3>;
- vdd33a-supply = <&fixedregulator3v3>;
- };
-};
diff --git a/trunk/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/trunk/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
deleted file mode 100644
index f33b5ccb7446..000000000000
--- a/trunk/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Device Tree Source for the KZM-A9-GT board
- *
- * Copyright (C) 2012 Horms Solutions Ltd.
- *
- * Based on sh73a0-kzm9g.dts
- * Copyright (C) 2012 Renesas Solutions Corp.
- *
- * This file is licensed under the terms of the GNU General Public License
- * version 2. This program is licensed "as is" without any warranty of any
- * kind, whether express or implied.
- */
-
-/dts-v1/;
-/include/ "sh73a0.dtsi"
-
-/ {
- model = "KZM-A9-GT";
- compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
-
- chosen {
- bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200";
- };
-
- memory {
- device_type = "memory";
- reg = <0x41000000 0x1e800000>;
- };
-
- reg_1p8v: regulator@0 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- regulator-boot-on;
- };
-
- reg_3p3v: regulator@1 {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-always-on;
- regulator-boot-on;
- };
-};
-
-&mmcif {
- bus-width = <8>;
- vmmc-supply = <®_1p8v>;
- status = "okay";
-};
-
-&sdhi0 {
- vmmc-supply = <®_3p3v>;
- bus-width = <4>;
- status = "okay";
-};
-
-&sdhi2 {
- vmmc-supply = <®_3p3v>;
- bus-width = <4>;
- broken-cd;
- status = "okay";
-};
diff --git a/trunk/arch/arm/boot/dts/sh73a0-reference.dtsi b/trunk/arch/arm/boot/dts/sh73a0-reference.dtsi
new file mode 100644
index 000000000000..d4bb0125b2b2
--- /dev/null
+++ b/trunk/arch/arm/boot/dts/sh73a0-reference.dtsi
@@ -0,0 +1,24 @@
+/*
+ * Device Tree Source for the SH73A0 SoC
+ *
+ * Copyright (C) 2012 Renesas Solutions Corp.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/include/ "sh73a0.dtsi"
+
+/ {
+ compatible = "renesas,sh73a0";
+
+ mmcif: mmcif@0x10010000 {
+ compatible = "renesas,sh-mmcif";
+ reg = <0xe6bd0000 0x100>;
+ interrupt-parent = <&gic>;
+ interrupts = <0 140 0x4
+ 0 141 0x4>;
+ reg-io-width = <4>;
+ };
+};
diff --git a/trunk/arch/arm/boot/dts/sh73a0.dtsi b/trunk/arch/arm/boot/dts/sh73a0.dtsi
index 3e4d383ac6d9..8a59465d0231 100644
--- a/trunk/arch/arm/boot/dts/sh73a0.dtsi
+++ b/trunk/arch/arm/boot/dts/sh73a0.dtsi
@@ -97,48 +97,4 @@
0 189 0x4
0 190 0x4>;
};
-
- mmcif: mmcif@0x10010000 {
- compatible = "renesas,sh-mmcif";
- reg = <0xe6bd0000 0x100>;
- interrupt-parent = <&gic>;
- interrupts = <0 140 0x4
- 0 141 0x4>;
- reg-io-width = <4>;
- status = "disabled";
- };
-
- sdhi0: sdhi@0xee100000 {
- compatible = "renesas,r8a7740-sdhi";
- reg = <0xee100000 0x100>;
- interrupt-parent = <&gic>;
- interrupts = <0 83 4
- 0 84 4
- 0 85 4>;
- cap-sd-highspeed;
- status = "disabled";
- };
-
- /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
- sdhi1: sdhi@0xee120000 {
- compatible = "renesas,r8a7740-sdhi";
- reg = <0xee120000 0x100>;
- interrupt-parent = <&gic>;
- interrupts = <0 88 4
- 0 89 4>;
- toshiba,mmc-wrprotect-disable;
- cap-sd-highspeed;
- status = "disabled";
- };
-
- sdhi2: sdhi@0xee140000 {
- compatible = "renesas,r8a7740-sdhi";
- reg = <0xee140000 0x100>;
- interrupt-parent = <&gic>;
- interrupts = <0 104 4
- 0 105 4>;
- toshiba,mmc-wrprotect-disable;
- cap-sd-highspeed;
- status = "disabled";
- };
};
diff --git a/trunk/arch/arm/boot/dts/tegra114-dalmore.dts b/trunk/arch/arm/boot/dts/tegra114-dalmore.dts
index 616990dc92db..6ebc1b704190 100644
--- a/trunk/arch/arm/boot/dts/tegra114-dalmore.dts
+++ b/trunk/arch/arm/boot/dts/tegra114-dalmore.dts
@@ -12,6 +12,7 @@
serial@70006300 {
status = "okay";
+ clock-frequency = <408000000>;
};
pmc {
diff --git a/trunk/arch/arm/boot/dts/tegra114-pluto.dts b/trunk/arch/arm/boot/dts/tegra114-pluto.dts
index 6bbc8efae9c0..5deb8692b350 100644
--- a/trunk/arch/arm/boot/dts/tegra114-pluto.dts
+++ b/trunk/arch/arm/boot/dts/tegra114-pluto.dts
@@ -12,6 +12,7 @@
serial@70006300 {
status = "okay";
+ clock-frequency = <408000000>;
};
pmc {
diff --git a/trunk/arch/arm/boot/dts/tegra114.dtsi b/trunk/arch/arm/boot/dts/tegra114.dtsi
index c1110a9b2a91..c0b527d15fda 100644
--- a/trunk/arch/arm/boot/dts/tegra114.dtsi
+++ b/trunk/arch/arm/boot/dts/tegra114.dtsi
@@ -24,11 +24,10 @@
0 42 0x04
0 121 0x04
0 122 0x04>;
- clocks = <&tegra_car 5>;
};
tegra_car: clock {
- compatible = "nvidia,tegra114-car";
+ compatible = "nvidia,tegra114-car, nvidia,tegra30-car";
reg = <0x60006000 0x1000>;
#clock-cells = <1>;
};
@@ -67,7 +66,6 @@
reg-shift = <2>;
interrupts = <0 36 0x04>;
status = "disabled";
- clocks = <&tegra_car 6>;
};
serial@70006040 {
@@ -76,7 +74,6 @@
reg-shift = <2>;
interrupts = <0 37 0x04>;
status = "disabled";
- clocks = <&tegra_car 192>;
};
serial@70006200 {
@@ -85,7 +82,6 @@
reg-shift = <2>;
interrupts = <0 46 0x04>;
status = "disabled";
- clocks = <&tegra_car 55>;
};
serial@70006300 {
@@ -94,14 +90,12 @@
reg-shift = <2>;
interrupts = <0 90 0x04>;
status = "disabled";
- clocks = <&tegra_car 65>;
};
rtc {
compatible = "nvidia,tegra114-rtc", "nvidia,tegra20-rtc";
reg = <0x7000e000 0x100>;
interrupts = <0 2 0x04>;
- clocks = <&tegra_car 4>;
};
pmc {
diff --git a/trunk/arch/arm/boot/dts/vt8500.dtsi b/trunk/arch/arm/boot/dts/vt8500.dtsi
index 4a4b96f6827e..68c8dc644383 100644
--- a/trunk/arch/arm/boot/dts/vt8500.dtsi
+++ b/trunk/arch/arm/boot/dts/vt8500.dtsi
@@ -25,13 +25,11 @@
#interrupt-cells = <1>;
};
- pinctrl: pinctrl@d8110000 {
- compatible = "via,vt8500-pinctrl";
- reg = <0xd8110000 0x10000>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ gpio: gpio-controller@d8110000 {
+ compatible = "via,vt8500-gpio";
gpio-controller;
- #gpio-cells = <2>;
+ reg = <0xd8110000 0x10000>;
+ #gpio-cells = <3>;
};
pmc@d8130000 {
diff --git a/trunk/arch/arm/boot/dts/wm8505.dtsi b/trunk/arch/arm/boot/dts/wm8505.dtsi
index b2bf359e852f..398b8bca791e 100644
--- a/trunk/arch/arm/boot/dts/wm8505.dtsi
+++ b/trunk/arch/arm/boot/dts/wm8505.dtsi
@@ -40,13 +40,11 @@
interrupts = <56 57 58 59 60 61 62 63>;
};
- pinctrl: pinctrl@d8110000 {
- compatible = "wm,wm8505-pinctrl";
- reg = <0xd8110000 0x10000>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ gpio: gpio-controller@d8110000 {
+ compatible = "wm,wm8505-gpio";
gpio-controller;
- #gpio-cells = <2>;
+ reg = <0xd8110000 0x10000>;
+ #gpio-cells = <3>;
};
pmc@d8130000 {
diff --git a/trunk/arch/arm/boot/dts/wm8650.dtsi b/trunk/arch/arm/boot/dts/wm8650.dtsi
index dd8464eeb40d..9313407bbc30 100644
--- a/trunk/arch/arm/boot/dts/wm8650.dtsi
+++ b/trunk/arch/arm/boot/dts/wm8650.dtsi
@@ -34,13 +34,11 @@
interrupts = <56 57 58 59 60 61 62 63>;
};
- pinctrl: pinctrl@d8110000 {
- compatible = "wm,wm8650-pinctrl";
- reg = <0xd8110000 0x10000>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ gpio: gpio-controller@d8110000 {
+ compatible = "wm,wm8650-gpio";
gpio-controller;
- #gpio-cells = <2>;
+ reg = <0xd8110000 0x10000>;
+ #gpio-cells = <3>;
};
pmc@d8130000 {
diff --git a/trunk/arch/arm/boot/dts/wm8850.dtsi b/trunk/arch/arm/boot/dts/wm8850.dtsi
index fc790d0aee66..7149cd13e3b9 100644
--- a/trunk/arch/arm/boot/dts/wm8850.dtsi
+++ b/trunk/arch/arm/boot/dts/wm8850.dtsi
@@ -41,13 +41,11 @@
interrupts = <56 57 58 59 60 61 62 63>;
};
- pinctrl: pinctrl@d8110000 {
- compatible = "wm,wm8850-pinctrl";
- reg = <0xd8110000 0x10000>;
- interrupt-controller;
- #interrupt-cells = <2>;
+ gpio: gpio-controller@d8110000 {
+ compatible = "wm,wm8650-gpio";
gpio-controller;
- #gpio-cells = <2>;
+ reg = <0xd8110000 0x10000>;
+ #gpio-cells = <3>;
};
pmc@d8130000 {
diff --git a/trunk/arch/arm/boot/dts/zynq-7000.dtsi b/trunk/arch/arm/boot/dts/zynq-7000.dtsi
index 748fc347ed18..9e1c339c4491 100644
--- a/trunk/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/trunk/arch/arm/boot/dts/zynq-7000.dtsi
@@ -118,23 +118,56 @@
};
ttc0: ttc0@f8001000 {
- interrupt-parent = <&intc>;
- interrupts = < 0 10 4 0 11 4 0 12 4 >;
- compatible = "cdns,ttc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "xlnx,ttc";
reg = <0xF8001000 0x1000>;
clocks = <&cpu_clk 3>;
clock-names = "cpu_1x";
clock-ranges;
+
+ ttc0_0: ttc0.0 {
+ status = "disabled";
+ reg = <0>;
+ interrupts = <0 10 4>;
+ };
+ ttc0_1: ttc0.1 {
+ status = "disabled";
+ reg = <1>;
+ interrupts = <0 11 4>;
+ };
+ ttc0_2: ttc0.2 {
+ status = "disabled";
+ reg = <2>;
+ interrupts = <0 12 4>;
+ };
};
ttc1: ttc1@f8002000 {
- interrupt-parent = <&intc>;
- interrupts = < 0 37 4 0 38 4 0 39 4 >;
- compatible = "cdns,ttc";
+ #interrupt-parent = <&intc>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "xlnx,ttc";
reg = <0xF8002000 0x1000>;
clocks = <&cpu_clk 3>;
clock-names = "cpu_1x";
clock-ranges;
+
+ ttc1_0: ttc1.0 {
+ status = "disabled";
+ reg = <0>;
+ interrupts = <0 37 4>;
+ };
+ ttc1_1: ttc1.1 {
+ status = "disabled";
+ reg = <1>;
+ interrupts = <0 38 4>;
+ };
+ ttc1_2: ttc1.2 {
+ status = "disabled";
+ reg = <2>;
+ interrupts = <0 39 4>;
+ };
};
};
};
diff --git a/trunk/arch/arm/boot/dts/zynq-zc702.dts b/trunk/arch/arm/boot/dts/zynq-zc702.dts
index 86f44d5b0265..c772942a399a 100644
--- a/trunk/arch/arm/boot/dts/zynq-zc702.dts
+++ b/trunk/arch/arm/boot/dts/zynq-zc702.dts
@@ -32,3 +32,13 @@
&ps_clk {
clock-frequency = <33333330>;
};
+
+&ttc0_0 {
+ status = "ok";
+ compatible = "xlnx,ttc-counter-clocksource";
+};
+
+&ttc0_1 {
+ status = "ok";
+ compatible = "xlnx,ttc-counter-clockevent";
+};
diff --git a/trunk/arch/arm/common/Makefile b/trunk/arch/arm/common/Makefile
index 48434cbe3e89..dc8dd0de5c0f 100644
--- a/trunk/arch/arm/common/Makefile
+++ b/trunk/arch/arm/common/Makefile
@@ -2,8 +2,6 @@
# Makefile for the linux kernel.
#
-obj-y += firmware.o
-
obj-$(CONFIG_ICST) += icst.o
obj-$(CONFIG_SA1111) += sa1111.o
obj-$(CONFIG_PCI_HOST_VIA82C505) += via82c505.o
@@ -13,6 +11,3 @@ obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
obj-$(CONFIG_SHARP_SCOOP) += scoop.o
obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
obj-$(CONFIG_ARM_TIMER_SP804) += timer-sp.o
-obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
-AFLAGS_mcpm_head.o := -march=armv7-a
-AFLAGS_vlock.o := -march=armv7-a
diff --git a/trunk/arch/arm/common/firmware.c b/trunk/arch/arm/common/firmware.c
deleted file mode 100644
index 27ddccb1131f..000000000000
--- a/trunk/arch/arm/common/firmware.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics.
- * Kyungmin Park
- * Tomasz Figa
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include
-#include
-
-#include
-
-static const struct firmware_ops default_firmware_ops;
-
-const struct firmware_ops *firmware_ops = &default_firmware_ops;
diff --git a/trunk/arch/arm/common/mcpm_entry.c b/trunk/arch/arm/common/mcpm_entry.c
deleted file mode 100644
index 370236dd1a03..000000000000
--- a/trunk/arch/arm/common/mcpm_entry.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * arch/arm/common/mcpm_entry.c -- entry point for multi-cluster PM
- *
- * Created by: Nicolas Pitre, March 2012
- * Copyright: (C) 2012-2013 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include
-#include
-#include
-
-#include
-#include
-#include
-#include
-
-extern unsigned long mcpm_entry_vectors[MAX_NR_CLUSTERS][MAX_CPUS_PER_CLUSTER];
-
-void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr)
-{
- unsigned long val = ptr ? virt_to_phys(ptr) : 0;
- mcpm_entry_vectors[cluster][cpu] = val;
- sync_cache_w(&mcpm_entry_vectors[cluster][cpu]);
-}
-
-static const struct mcpm_platform_ops *platform_ops;
-
-int __init mcpm_platform_register(const struct mcpm_platform_ops *ops)
-{
- if (platform_ops)
- return -EBUSY;
- platform_ops = ops;
- return 0;
-}
-
-int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster)
-{
- if (!platform_ops)
- return -EUNATCH; /* try not to shadow power_up errors */
- might_sleep();
- return platform_ops->power_up(cpu, cluster);
-}
-
-typedef void (*phys_reset_t)(unsigned long);
-
-void mcpm_cpu_power_down(void)
-{
- phys_reset_t phys_reset;
-
- BUG_ON(!platform_ops);
- BUG_ON(!irqs_disabled());
-
- /*
- * Do this before calling into the power_down method,
- * as it might not always be safe to do afterwards.
- */
- setup_mm_for_reboot();
-
- platform_ops->power_down();
-
- /*
- * It is possible for a power_up request to happen concurrently
- * with a power_down request for the same CPU. In this case the
- * power_down method might not be able to actually enter a
- * powered down state with the WFI instruction if the power_up
- * method has removed the required reset condition. The
- * power_down method is then allowed to return. We must perform
- * a re-entry in the kernel as if the power_up method just had
- * deasserted reset on the CPU.
- *
- * To simplify race issues, the platform specific implementation
- * must accommodate for the possibility of unordered calls to
- * power_down and power_up with a usage count. Therefore, if a
- * call to power_up is issued for a CPU that is not down, then
- * the next call to power_down must not attempt a full shutdown
- * but only do the minimum (normally disabling L1 cache and CPU
- * coherency) and return just as if a concurrent power_up request
- * had happened as described above.
- */
-
- phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
- phys_reset(virt_to_phys(mcpm_entry_point));
-
- /* should never get here */
- BUG();
-}
-
-void mcpm_cpu_suspend(u64 expected_residency)
-{
- phys_reset_t phys_reset;
-
- BUG_ON(!platform_ops);
- BUG_ON(!irqs_disabled());
-
- /* Very similar to mcpm_cpu_power_down() */
- setup_mm_for_reboot();
- platform_ops->suspend(expected_residency);
- phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
- phys_reset(virt_to_phys(mcpm_entry_point));
- BUG();
-}
-
-int mcpm_cpu_powered_up(void)
-{
- if (!platform_ops)
- return -EUNATCH;
- if (platform_ops->powered_up)
- platform_ops->powered_up();
- return 0;
-}
-
-struct sync_struct mcpm_sync;
-
-/*
- * __mcpm_cpu_going_down: Indicates that the cpu is being torn down.
- * This must be called at the point of committing to teardown of a CPU.
- * The CPU cache (SCTRL.C bit) is expected to still be active.
- */
-void __mcpm_cpu_going_down(unsigned int cpu, unsigned int cluster)
-{
- mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_GOING_DOWN;
- sync_cache_w(&mcpm_sync.clusters[cluster].cpus[cpu].cpu);
-}
-
-/*
- * __mcpm_cpu_down: Indicates that cpu teardown is complete and that the
- * cluster can be torn down without disrupting this CPU.
- * To avoid deadlocks, this must be called before a CPU is powered down.
- * The CPU cache (SCTRL.C bit) is expected to be off.
- * However L2 cache might or might not be active.
- */
-void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster)
-{
- dmb();
- mcpm_sync.clusters[cluster].cpus[cpu].cpu = CPU_DOWN;
- sync_cache_w(&mcpm_sync.clusters[cluster].cpus[cpu].cpu);
- dsb_sev();
-}
-
-/*
- * __mcpm_outbound_leave_critical: Leave the cluster teardown critical section.
- * @state: the final state of the cluster:
- * CLUSTER_UP: no destructive teardown was done and the cluster has been
- * restored to the previous state (CPU cache still active); or
- * CLUSTER_DOWN: the cluster has been torn-down, ready for power-off
- * (CPU cache disabled, L2 cache either enabled or disabled).
- */
-void __mcpm_outbound_leave_critical(unsigned int cluster, int state)
-{
- dmb();
- mcpm_sync.clusters[cluster].cluster = state;
- sync_cache_w(&mcpm_sync.clusters[cluster].cluster);
- dsb_sev();
-}
-
-/*
- * __mcpm_outbound_enter_critical: Enter the cluster teardown critical section.
- * This function should be called by the last man, after local CPU teardown
- * is complete. CPU cache expected to be active.
- *
- * Returns:
- * false: the critical section was not entered because an inbound CPU was
- * observed, or the cluster is already being set up;
- * true: the critical section was entered: it is now safe to tear down the
- * cluster.
- */
-bool __mcpm_outbound_enter_critical(unsigned int cpu, unsigned int cluster)
-{
- unsigned int i;
- struct mcpm_sync_struct *c = &mcpm_sync.clusters[cluster];
-
- /* Warn inbound CPUs that the cluster is being torn down: */
- c->cluster = CLUSTER_GOING_DOWN;
- sync_cache_w(&c->cluster);
-
- /* Back out if the inbound cluster is already in the critical region: */
- sync_cache_r(&c->inbound);
- if (c->inbound == INBOUND_COMING_UP)
- goto abort;
-
- /*
- * Wait for all CPUs to get out of the GOING_DOWN state, so that local
- * teardown is complete on each CPU before tearing down the cluster.
- *
- * If any CPU has been woken up again from the DOWN state, then we
- * shouldn't be taking the cluster down at all: abort in that case.
- */
- sync_cache_r(&c->cpus);
- for (i = 0; i < MAX_CPUS_PER_CLUSTER; i++) {
- int cpustate;
-
- if (i == cpu)
- continue;
-
- while (1) {
- cpustate = c->cpus[i].cpu;
- if (cpustate != CPU_GOING_DOWN)
- break;
-
- wfe();
- sync_cache_r(&c->cpus[i].cpu);
- }
-
- switch (cpustate) {
- case CPU_DOWN:
- continue;
-
- default:
- goto abort;
- }
- }
-
- return true;
-
-abort:
- __mcpm_outbound_leave_critical(cluster, CLUSTER_UP);
- return false;
-}
-
-int __mcpm_cluster_state(unsigned int cluster)
-{
- sync_cache_r(&mcpm_sync.clusters[cluster].cluster);
- return mcpm_sync.clusters[cluster].cluster;
-}
-
-extern unsigned long mcpm_power_up_setup_phys;
-
-int __init mcpm_sync_init(
- void (*power_up_setup)(unsigned int affinity_level))
-{
- unsigned int i, j, mpidr, this_cluster;
-
- BUILD_BUG_ON(MCPM_SYNC_CLUSTER_SIZE * MAX_NR_CLUSTERS != sizeof mcpm_sync);
- BUG_ON((unsigned long)&mcpm_sync & (__CACHE_WRITEBACK_GRANULE - 1));
-
- /*
- * Set initial CPU and cluster states.
- * Only one cluster is assumed to be active at this point.
- */
- for (i = 0; i < MAX_NR_CLUSTERS; i++) {
- mcpm_sync.clusters[i].cluster = CLUSTER_DOWN;
- mcpm_sync.clusters[i].inbound = INBOUND_NOT_COMING_UP;
- for (j = 0; j < MAX_CPUS_PER_CLUSTER; j++)
- mcpm_sync.clusters[i].cpus[j].cpu = CPU_DOWN;
- }
- mpidr = read_cpuid_mpidr();
- this_cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
- for_each_online_cpu(i)
- mcpm_sync.clusters[this_cluster].cpus[i].cpu = CPU_UP;
- mcpm_sync.clusters[this_cluster].cluster = CLUSTER_UP;
- sync_cache_w(&mcpm_sync);
-
- if (power_up_setup) {
- mcpm_power_up_setup_phys = virt_to_phys(power_up_setup);
- sync_cache_w(&mcpm_power_up_setup_phys);
- }
-
- return 0;
-}
diff --git a/trunk/arch/arm/common/mcpm_head.S b/trunk/arch/arm/common/mcpm_head.S
deleted file mode 100644
index 8178705c4b24..000000000000
--- a/trunk/arch/arm/common/mcpm_head.S
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * arch/arm/common/mcpm_head.S -- kernel entry point for multi-cluster PM
- *
- * Created by: Nicolas Pitre, March 2012
- * Copyright: (C) 2012-2013 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- *
- * Refer to Documentation/arm/cluster-pm-race-avoidance.txt
- * for details of the synchronisation algorithms used here.
- */
-
-#include
-#include
-
-#include "vlock.h"
-
-.if MCPM_SYNC_CLUSTER_CPUS
-.error "cpus must be the first member of struct mcpm_sync_struct"
-.endif
-
- .macro pr_dbg string
-#if defined(CONFIG_DEBUG_LL) && defined(DEBUG)
- b 1901f
-1902: .asciz "CPU"
-1903: .asciz " cluster"
-1904: .asciz ": \string"
- .align
-1901: adr r0, 1902b
- bl printascii
- mov r0, r9
- bl printhex8
- adr r0, 1903b
- bl printascii
- mov r0, r10
- bl printhex8
- adr r0, 1904b
- bl printascii
-#endif
- .endm
-
- .arm
- .align
-
-ENTRY(mcpm_entry_point)
-
- THUMB( adr r12, BSYM(1f) )
- THUMB( bx r12 )
- THUMB( .thumb )
-1:
- mrc p15, 0, r0, c0, c0, 5 @ MPIDR
- ubfx r9, r0, #0, #8 @ r9 = cpu
- ubfx r10, r0, #8, #8 @ r10 = cluster
- mov r3, #MAX_CPUS_PER_CLUSTER
- mla r4, r3, r10, r9 @ r4 = canonical CPU index
- cmp r4, #(MAX_CPUS_PER_CLUSTER * MAX_NR_CLUSTERS)
- blo 2f
-
- /* We didn't expect this CPU. Try to cheaply make it quiet. */
-1: wfi
- wfe
- b 1b
-
-2: pr_dbg "kernel mcpm_entry_point\n"
-
- /*
- * MMU is off so we need to get to various variables in a
- * position independent way.
- */
- adr r5, 3f
- ldmia r5, {r6, r7, r8, r11}
- add r6, r5, r6 @ r6 = mcpm_entry_vectors
- ldr r7, [r5, r7] @ r7 = mcpm_power_up_setup_phys
- add r8, r5, r8 @ r8 = mcpm_sync
- add r11, r5, r11 @ r11 = first_man_locks
-
- mov r0, #MCPM_SYNC_CLUSTER_SIZE
- mla r8, r0, r10, r8 @ r8 = sync cluster base
-
- @ Signal that this CPU is coming UP:
- mov r0, #CPU_COMING_UP
- mov r5, #MCPM_SYNC_CPU_SIZE
- mla r5, r9, r5, r8 @ r5 = sync cpu address
- strb r0, [r5]
-
- @ At this point, the cluster cannot unexpectedly enter the GOING_DOWN
- @ state, because there is at least one active CPU (this CPU).
-
- mov r0, #VLOCK_SIZE
- mla r11, r0, r10, r11 @ r11 = cluster first man lock
- mov r0, r11
- mov r1, r9 @ cpu
- bl vlock_trylock @ implies DMB
-
- cmp r0, #0 @ failed to get the lock?
- bne mcpm_setup_wait @ wait for cluster setup if so
-
- ldrb r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
- cmp r0, #CLUSTER_UP @ cluster already up?
- bne mcpm_setup @ if not, set up the cluster
-
- @ Otherwise, release the first man lock and skip setup:
- mov r0, r11
- bl vlock_unlock
- b mcpm_setup_complete
-
-mcpm_setup:
- @ Control dependency implies strb not observable before previous ldrb.
-
- @ Signal that the cluster is being brought up:
- mov r0, #INBOUND_COMING_UP
- strb r0, [r8, #MCPM_SYNC_CLUSTER_INBOUND]
- dmb
-
- @ Any CPU trying to take the cluster into CLUSTER_GOING_DOWN from this
- @ point onwards will observe INBOUND_COMING_UP and abort.
-
- @ Wait for any previously-pending cluster teardown operations to abort
- @ or complete:
-mcpm_teardown_wait:
- ldrb r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
- cmp r0, #CLUSTER_GOING_DOWN
- bne first_man_setup
- wfe
- b mcpm_teardown_wait
-
-first_man_setup:
- dmb
-
- @ If the outbound gave up before teardown started, skip cluster setup:
-
- cmp r0, #CLUSTER_UP
- beq mcpm_setup_leave
-
- @ power_up_setup is now responsible for setting up the cluster:
-
- cmp r7, #0
- mov r0, #1 @ second (cluster) affinity level
- blxne r7 @ Call power_up_setup if defined
- dmb
-
- mov r0, #CLUSTER_UP
- strb r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
- dmb
-
-mcpm_setup_leave:
- @ Leave the cluster setup critical section:
-
- mov r0, #INBOUND_NOT_COMING_UP
- strb r0, [r8, #MCPM_SYNC_CLUSTER_INBOUND]
- dsb
- sev
-
- mov r0, r11
- bl vlock_unlock @ implies DMB
- b mcpm_setup_complete
-
- @ In the contended case, non-first men wait here for cluster setup
- @ to complete:
-mcpm_setup_wait:
- ldrb r0, [r8, #MCPM_SYNC_CLUSTER_CLUSTER]
- cmp r0, #CLUSTER_UP
- wfene
- bne mcpm_setup_wait
- dmb
-
-mcpm_setup_complete:
- @ If a platform-specific CPU setup hook is needed, it is
- @ called from here.
-
- cmp r7, #0
- mov r0, #0 @ first (CPU) affinity level
- blxne r7 @ Call power_up_setup if defined
- dmb
-
- @ Mark the CPU as up:
-
- mov r0, #CPU_UP
- strb r0, [r5]
-
- @ Observability order of CPU_UP and opening of the gate does not matter.
-
-mcpm_entry_gated:
- ldr r5, [r6, r4, lsl #2] @ r5 = CPU entry vector
- cmp r5, #0
- wfeeq
- beq mcpm_entry_gated
- dmb
-
- pr_dbg "released\n"
- bx r5
-
- .align 2
-
-3: .word mcpm_entry_vectors - .
- .word mcpm_power_up_setup_phys - 3b
- .word mcpm_sync - 3b
- .word first_man_locks - 3b
-
-ENDPROC(mcpm_entry_point)
-
- .bss
-
- .align CACHE_WRITEBACK_ORDER
- .type first_man_locks, #object
-first_man_locks:
- .space VLOCK_SIZE * MAX_NR_CLUSTERS
- .align CACHE_WRITEBACK_ORDER
-
- .type mcpm_entry_vectors, #object
-ENTRY(mcpm_entry_vectors)
- .space 4 * MAX_NR_CLUSTERS * MAX_CPUS_PER_CLUSTER
-
- .type mcpm_power_up_setup_phys, #object
-ENTRY(mcpm_power_up_setup_phys)
- .space 4 @ set by mcpm_sync_init()
diff --git a/trunk/arch/arm/common/mcpm_platsmp.c b/trunk/arch/arm/common/mcpm_platsmp.c
deleted file mode 100644
index 52b88d81b7bb..000000000000
--- a/trunk/arch/arm/common/mcpm_platsmp.c
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * linux/arch/arm/mach-vexpress/mcpm_platsmp.c
- *
- * Created by: Nicolas Pitre, November 2012
- * Copyright: (C) 2012-2013 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Code to handle secondary CPU bringup and hotplug for the cluster power API.
- */
-
-#include
-#include
-#include
-
-#include
-
-#include
-#include
-#include
-
-static void __init simple_smp_init_cpus(void)
-{
-}
-
-static int __cpuinit mcpm_boot_secondary(unsigned int cpu, struct task_struct *idle)
-{
- unsigned int mpidr, pcpu, pcluster, ret;
- extern void secondary_startup(void);
-
- mpidr = cpu_logical_map(cpu);
- pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
- pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
- pr_debug("%s: logical CPU %d is physical CPU %d cluster %d\n",
- __func__, cpu, pcpu, pcluster);
-
- mcpm_set_entry_vector(pcpu, pcluster, NULL);
- ret = mcpm_cpu_power_up(pcpu, pcluster);
- if (ret)
- return ret;
- mcpm_set_entry_vector(pcpu, pcluster, secondary_startup);
- arch_send_wakeup_ipi_mask(cpumask_of(cpu));
- dsb_sev();
- return 0;
-}
-
-static void __cpuinit mcpm_secondary_init(unsigned int cpu)
-{
- mcpm_cpu_powered_up();
- gic_secondary_init(0);
-}
-
-#ifdef CONFIG_HOTPLUG_CPU
-
-static int mcpm_cpu_disable(unsigned int cpu)
-{
- /*
- * We assume all CPUs may be shut down.
- * This would be the hook to use for eventual Secure
- * OS migration requests as described in the PSCI spec.
- */
- return 0;
-}
-
-static void mcpm_cpu_die(unsigned int cpu)
-{
- unsigned int mpidr, pcpu, pcluster;
- mpidr = read_cpuid_mpidr();
- pcpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
- pcluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
- mcpm_set_entry_vector(pcpu, pcluster, NULL);
- mcpm_cpu_power_down();
-}
-
-#endif
-
-static struct smp_operations __initdata mcpm_smp_ops = {
- .smp_init_cpus = simple_smp_init_cpus,
- .smp_boot_secondary = mcpm_boot_secondary,
- .smp_secondary_init = mcpm_secondary_init,
-#ifdef CONFIG_HOTPLUG_CPU
- .cpu_disable = mcpm_cpu_disable,
- .cpu_die = mcpm_cpu_die,
-#endif
-};
-
-void __init mcpm_smp_set_ops(void)
-{
- smp_set_ops(&mcpm_smp_ops);
-}
diff --git a/trunk/arch/arm/common/vlock.S b/trunk/arch/arm/common/vlock.S
deleted file mode 100644
index ff198583f683..000000000000
--- a/trunk/arch/arm/common/vlock.S
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * vlock.S - simple voting lock implementation for ARM
- *
- * Created by: Dave Martin, 2012-08-16
- * Copyright: (C) 2012-2013 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- *
- * This algorithm is described in more detail in
- * Documentation/arm/vlocks.txt.
- */
-
-#include
-#include "vlock.h"
-
-/* Select different code if voting flags can fit in a single word. */
-#if VLOCK_VOTING_SIZE > 4
-#define FEW(x...)
-#define MANY(x...) x
-#else
-#define FEW(x...) x
-#define MANY(x...)
-#endif
-
-@ voting lock for first-man coordination
-
-.macro voting_begin rbase:req, rcpu:req, rscratch:req
- mov \rscratch, #1
- strb \rscratch, [\rbase, \rcpu]
- dmb
-.endm
-
-.macro voting_end rbase:req, rcpu:req, rscratch:req
- dmb
- mov \rscratch, #0
- strb \rscratch, [\rbase, \rcpu]
- dsb
- sev
-.endm
-
-/*
- * The vlock structure must reside in Strongly-Ordered or Device memory.
- * This implementation deliberately eliminates most of the barriers which
- * would be required for other memory types, and assumes that independent
- * writes to neighbouring locations within a cacheline do not interfere
- * with one another.
- */
-
-@ r0: lock structure base
-@ r1: CPU ID (0-based index within cluster)
-ENTRY(vlock_trylock)
- add r1, r1, #VLOCK_VOTING_OFFSET
-
- voting_begin r0, r1, r2
-
- ldrb r2, [r0, #VLOCK_OWNER_OFFSET] @ check whether lock is held
- cmp r2, #VLOCK_OWNER_NONE
- bne trylock_fail @ fail if so
-
- @ Control dependency implies strb not observable before previous ldrb.
-
- strb r1, [r0, #VLOCK_OWNER_OFFSET] @ submit my vote
-
- voting_end r0, r1, r2 @ implies DMB
-
- @ Wait for the current round of voting to finish:
-
- MANY( mov r3, #VLOCK_VOTING_OFFSET )
-0:
- MANY( ldr r2, [r0, r3] )
- FEW( ldr r2, [r0, #VLOCK_VOTING_OFFSET] )
- cmp r2, #0
- wfene
- bne 0b
- MANY( add r3, r3, #4 )
- MANY( cmp r3, #VLOCK_VOTING_OFFSET + VLOCK_VOTING_SIZE )
- MANY( bne 0b )
-
- @ Check who won:
-
- dmb
- ldrb r2, [r0, #VLOCK_OWNER_OFFSET]
- eor r0, r1, r2 @ zero if I won, else nonzero
- bx lr
-
-trylock_fail:
- voting_end r0, r1, r2
- mov r0, #1 @ nonzero indicates that I lost
- bx lr
-ENDPROC(vlock_trylock)
-
-@ r0: lock structure base
-ENTRY(vlock_unlock)
- dmb
- mov r1, #VLOCK_OWNER_NONE
- strb r1, [r0, #VLOCK_OWNER_OFFSET]
- dsb
- sev
- bx lr
-ENDPROC(vlock_unlock)
diff --git a/trunk/arch/arm/common/vlock.h b/trunk/arch/arm/common/vlock.h
deleted file mode 100644
index 3b441475a59b..000000000000
--- a/trunk/arch/arm/common/vlock.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * vlock.h - simple voting lock implementation
- *
- * Created by: Dave Martin, 2012-08-16
- * Copyright: (C) 2012-2013 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __VLOCK_H
-#define __VLOCK_H
-
-#include
-
-/* Offsets and sizes are rounded to a word (4 bytes) */
-#define VLOCK_OWNER_OFFSET 0
-#define VLOCK_VOTING_OFFSET 4
-#define VLOCK_VOTING_SIZE ((MAX_CPUS_PER_CLUSTER + 3) / 4 * 4)
-#define VLOCK_SIZE (VLOCK_VOTING_OFFSET + VLOCK_VOTING_SIZE)
-#define VLOCK_OWNER_NONE 0
-
-#endif /* ! __VLOCK_H */
diff --git a/trunk/arch/arm/configs/da8xx_omapl_defconfig b/trunk/arch/arm/configs/da8xx_omapl_defconfig
index 7c868139bdb0..9aaad36a1728 100644
--- a/trunk/arch/arm/configs/da8xx_omapl_defconfig
+++ b/trunk/arch/arm/configs/da8xx_omapl_defconfig
@@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_MODULES=y
diff --git a/trunk/arch/arm/configs/davinci_all_defconfig b/trunk/arch/arm/configs/davinci_all_defconfig
index c86fd75e181a..3edc78a40b66 100644
--- a/trunk/arch/arm/configs/davinci_all_defconfig
+++ b/trunk/arch/arm/configs/davinci_all_defconfig
@@ -5,7 +5,6 @@ CONFIG_POSIX_MQUEUE=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_LOG_BUF_SHIFT=14
-CONFIG_CGROUPS=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_MODULES=y
diff --git a/trunk/arch/arm/configs/kirkwood_defconfig b/trunk/arch/arm/configs/kirkwood_defconfig
index a1d8252e9ec7..3d8667f648b8 100644
--- a/trunk/arch/arm/configs/kirkwood_defconfig
+++ b/trunk/arch/arm/configs/kirkwood_defconfig
@@ -10,48 +10,45 @@ CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_KIRKWOOD=y
-CONFIG_MACH_D2NET_V2=y
CONFIG_MACH_DB88F6281_BP=y
-CONFIG_MACH_DOCKSTAR=y
-CONFIG_MACH_ESATA_SHEEVAPLUG=y
-CONFIG_MACH_GURUPLUG=y
-CONFIG_MACH_INETSPACE_V2=y
-CONFIG_MACH_MV88F6281GTW_GE=y
-CONFIG_MACH_NET2BIG_V2=y
-CONFIG_MACH_NET5BIG_V2=y
-CONFIG_MACH_NETSPACE_MAX_V2=y
-CONFIG_MACH_NETSPACE_V2=y
-CONFIG_MACH_OPENRD_BASE=y
-CONFIG_MACH_OPENRD_CLIENT=y
-CONFIG_MACH_OPENRD_ULTIMATE=y
CONFIG_MACH_RD88F6192_NAS=y
CONFIG_MACH_RD88F6281=y
+CONFIG_MACH_MV88F6281GTW_GE=y
CONFIG_MACH_SHEEVAPLUG=y
-CONFIG_MACH_T5325=y
-CONFIG_MACH_TS219=y
-CONFIG_MACH_TS41X=y
-CONFIG_MACH_CLOUDBOX_DT=y
+CONFIG_MACH_ESATA_SHEEVAPLUG=y
+CONFIG_MACH_GURUPLUG=y
+CONFIG_MACH_DREAMPLUG_DT=y
+CONFIG_MACH_ICONNECT_DT=y
CONFIG_MACH_DLINK_KIRKWOOD_DT=y
+CONFIG_MACH_IB62X0_DT=y
+CONFIG_MACH_TS219_DT=y
CONFIG_MACH_DOCKSTAR_DT=y
-CONFIG_MACH_DREAMPLUG_DT=y
CONFIG_MACH_GOFLEXNET_DT=y
-CONFIG_MACH_GURUPLUG_DT=y
-CONFIG_MACH_IB62X0_DT=y
-CONFIG_MACH_ICONNECT_DT=y
-CONFIG_MACH_INETSPACE_V2_DT=y
+CONFIG_MACH_LSXL_DT=y
CONFIG_MACH_IOMEGA_IX2_200_DT=y
CONFIG_MACH_KM_KIRKWOOD_DT=y
-CONFIG_MACH_LSXL_DT=y
+CONFIG_MACH_INETSPACE_V2_DT=y
CONFIG_MACH_MPLCEC4_DT=y
-CONFIG_MACH_NETSPACE_LITE_V2_DT=y
+CONFIG_MACH_NETSPACE_V2_DT=y
CONFIG_MACH_NETSPACE_MAX_V2_DT=y
+CONFIG_MACH_NETSPACE_LITE_V2_DT=y
CONFIG_MACH_NETSPACE_MINI_V2_DT=y
-CONFIG_MACH_NETSPACE_V2_DT=y
-CONFIG_MACH_NSA310_DT=y
CONFIG_MACH_OPENBLOCKS_A6_DT=y
-CONFIG_MACH_READYNAS_DT=y
CONFIG_MACH_TOPKICK_DT=y
-CONFIG_MACH_TS219_DT=y
+CONFIG_MACH_TS219=y
+CONFIG_MACH_TS41X=y
+CONFIG_MACH_DOCKSTAR=y
+CONFIG_MACH_OPENRD_BASE=y
+CONFIG_MACH_OPENRD_CLIENT=y
+CONFIG_MACH_OPENRD_ULTIMATE=y
+CONFIG_MACH_NETSPACE_V2=y
+CONFIG_MACH_INETSPACE_V2=y
+CONFIG_MACH_NETSPACE_MAX_V2=y
+CONFIG_MACH_D2NET_V2=y
+CONFIG_MACH_NET2BIG_V2=y
+CONFIG_MACH_NET5BIG_V2=y
+CONFIG_MACH_T5325=y
+CONFIG_MACH_NSA310_DT=y
# CONFIG_CPU_FEROCEON_OLD_ID is not set
CONFIG_PREEMPT=y
CONFIG_AEABI=y
diff --git a/trunk/arch/arm/configs/msm_defconfig b/trunk/arch/arm/configs/msm_defconfig
index 690b5f9c7462..2b8f7affc1eb 100644
--- a/trunk/arch/arm/configs/msm_defconfig
+++ b/trunk/arch/arm/configs/msm_defconfig
@@ -1,137 +1,72 @@
-CONFIG_SYSVIPC=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
+CONFIG_EXPERIMENTAL=y
CONFIG_IKCONFIG=y
CONFIG_IKCONFIG_PROC=y
CONFIG_BLK_DEV_INITRD=y
-CONFIG_SYSCTL_SYSCALL=y
-CONFIG_KALLSYMS_ALL=y
-CONFIG_EMBEDDED=y
-# CONFIG_SLUB_DEBUG is not set
-# CONFIG_COMPAT_BRK is not set
-CONFIG_PROFILING=y
-CONFIG_OPROFILE=y
-CONFIG_KPROBES=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PARTITION_ADVANCED=y
+CONFIG_SLAB=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
CONFIG_ARCH_MSM=y
-CONFIG_ARCH_MSM8X60=y
-CONFIG_ARCH_MSM8960=y
-CONFIG_SMP=y
+CONFIG_MACH_HALIBUT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
CONFIG_PREEMPT=y
CONFIG_AEABI=y
-CONFIG_HIGHMEM=y
-CONFIG_HIGHPTE=y
-CONFIG_CLEANCACHE=y
-CONFIG_CC_STACKPROTECTOR=y
-CONFIG_ARM_APPENDED_DTB=y
-CONFIG_ARM_ATAG_DTB_COMPAT=y
-CONFIG_AUTO_ZRELADDR=y
-CONFIG_VFP=y
-CONFIG_NEON=y
-# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_OABI_COMPAT is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="mem=64M console=ttyMSM,115200n8"
+CONFIG_PM=y
CONFIG_NET=y
-CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
-# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
-CONFIG_CFG80211=y
-CONFIG_RFKILL=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_SCSI=y
-CONFIG_SCSI_TGT=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-CONFIG_CHR_DEV_SCH=y
-CONFIG_SCSI_MULTI_LUN=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_MTD=y
+CONFIG_MTD_PARTITIONS=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
CONFIG_NETDEVICES=y
CONFIG_DUMMY=y
-CONFIG_PHYLIB=y
-CONFIG_SLIP=y
-CONFIG_SLIP_COMPRESSED=y
-CONFIG_SLIP_MODE_SLIP6=y
-CONFIG_USB_USBNET=y
-# CONFIG_USB_NET_AX8817X is not set
-# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_NET_ETHERNET=y
+CONFIG_SMC91X=y
+CONFIG_PPP=y
+CONFIG_PPP_ASYNC=y
+CONFIG_PPP_DEFLATE=y
+CONFIG_PPP_BSDCOMP=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
CONFIG_INPUT_EVDEV=y
# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_MOUSE_PS2 is not set
-CONFIG_INPUT_JOYSTICK=y
+# CONFIG_INPUT_MOUSE is not set
CONFIG_INPUT_TOUCHSCREEN=y
CONFIG_INPUT_MISC=y
-CONFIG_INPUT_UINPUT=y
-CONFIG_SERIO_LIBPS2=y
-# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
CONFIG_SERIAL_MSM=y
CONFIG_SERIAL_MSM_CONSOLE=y
-CONFIG_HW_RANDOM=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
-CONFIG_I2C_CHARDEV=y
-CONFIG_SPI=y
-CONFIG_SSBI=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_GPIO_SYSFS=y
-CONFIG_POWER_SUPPLY=y
-CONFIG_THERMAL=y
-CONFIG_REGULATOR=y
-CONFIG_MEDIA_SUPPORT=y
+# CONFIG_HWMON is not set
+CONFIG_VIDEO_OUTPUT_CONTROL=y
CONFIG_FB=y
-CONFIG_SOUND=y
-CONFIG_SND=y
-CONFIG_SND_DYNAMIC_MINORS=y
-# CONFIG_SND_ARM is not set
-# CONFIG_SND_SPI is not set
-# CONFIG_SND_USB is not set
-CONFIG_SND_SOC=y
-CONFIG_HID_BATTERY_STRENGTH=y
-CONFIG_USB=y
-CONFIG_USB_PHY=y
-CONFIG_USB_ANNOUNCE_NEW_DEVICES=y
-CONFIG_USB_MON=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_MSM=y
-CONFIG_USB_ACM=y
-CONFIG_USB_SERIAL=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DEBUG_FILES=y
-CONFIG_USB_GADGET_VBUS_DRAW=500
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+CONFIG_FB_MSM=y
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_NEW_LEDS=y
-CONFIG_RTC_CLASS=y
-CONFIG_STAGING=y
-CONFIG_MSM_IOMMU=y
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_EXT4_FS=y
-CONFIG_FUSE_FS=y
-CONFIG_VFAT_FS=y
+CONFIG_LEDS_CLASS=y
+CONFIG_INOTIFY=y
CONFIG_TMPFS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3_ACL=y
-CONFIG_NFS_V4=y
-CONFIG_CIFS=y
-CONFIG_PRINTK_TIME=y
CONFIG_MAGIC_SYSRQ=y
-CONFIG_LOCKUP_DETECTOR=y
-# CONFIG_DETECT_HUNG_TASK is not set
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_TIMER_STATS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_SCHEDSTATS=y
+CONFIG_DEBUG_MUTEXES=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
CONFIG_DEBUG_INFO=y
-CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_LL=y
diff --git a/trunk/arch/arm/configs/omap2plus_defconfig b/trunk/arch/arm/configs/omap2plus_defconfig
index 33903ca0d879..bd07864f14a0 100644
--- a/trunk/arch/arm/configs/omap2plus_defconfig
+++ b/trunk/arch/arm/configs/omap2plus_defconfig
@@ -93,7 +93,6 @@ CONFIG_BLK_DEV_RAM_SIZE=16384
CONFIG_SENSORS_LIS3LV02D=m
CONFIG_SENSORS_TSL2550=m
CONFIG_SENSORS_LIS3_I2C=m
-CONFIG_BMP085_I2C=m
CONFIG_SCSI=y
CONFIG_BLK_DEV_SD=y
CONFIG_SCSI_MULTI_LUN=y
diff --git a/trunk/arch/arm/include/asm/atomic.h b/trunk/arch/arm/include/asm/atomic.h
index da1c77d39327..c79f61faa3a5 100644
--- a/trunk/arch/arm/include/asm/atomic.h
+++ b/trunk/arch/arm/include/asm/atomic.h
@@ -243,29 +243,6 @@ typedef struct {
#define ATOMIC64_INIT(i) { (i) }
-#ifdef CONFIG_ARM_LPAE
-static inline u64 atomic64_read(const atomic64_t *v)
-{
- u64 result;
-
- __asm__ __volatile__("@ atomic64_read\n"
-" ldrd %0, %H0, [%1]"
- : "=&r" (result)
- : "r" (&v->counter), "Qo" (v->counter)
- );
-
- return result;
-}
-
-static inline void atomic64_set(atomic64_t *v, u64 i)
-{
- __asm__ __volatile__("@ atomic64_set\n"
-" strd %2, %H2, [%1]"
- : "=Qo" (v->counter)
- : "r" (&v->counter), "r" (i)
- );
-}
-#else
static inline u64 atomic64_read(const atomic64_t *v)
{
u64 result;
@@ -292,7 +269,6 @@ static inline void atomic64_set(atomic64_t *v, u64 i)
: "r" (&v->counter), "r" (i)
: "cc");
}
-#endif
static inline void atomic64_add(u64 i, atomic64_t *v)
{
diff --git a/trunk/arch/arm/include/asm/cacheflush.h b/trunk/arch/arm/include/asm/cacheflush.h
index bff71388e72a..e1489c54cd12 100644
--- a/trunk/arch/arm/include/asm/cacheflush.h
+++ b/trunk/arch/arm/include/asm/cacheflush.h
@@ -363,79 +363,4 @@ static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
flush_cache_all();
}
-/*
- * Memory synchronization helpers for mixed cached vs non cached accesses.
- *
- * Some synchronization algorithms have to set states in memory with the
- * cache enabled or disabled depending on the code path. It is crucial
- * to always ensure proper cache maintenance to update main memory right
- * away in that case.
- *
- * Any cached write must be followed by a cache clean operation.
- * Any cached read must be preceded by a cache invalidate operation.
- * Yet, in the read case, a cache flush i.e. atomic clean+invalidate
- * operation is needed to avoid discarding possible concurrent writes to the
- * accessed memory.
- *
- * Also, in order to prevent a cached writer from interfering with an
- * adjacent non-cached writer, each state variable must be located to
- * a separate cache line.
- */
-
-/*
- * This needs to be >= the max cache writeback size of all
- * supported platforms included in the current kernel configuration.
- * This is used to align state variables to their own cache lines.
- */
-#define __CACHE_WRITEBACK_ORDER 6 /* guessed from existing platforms */
-#define __CACHE_WRITEBACK_GRANULE (1 << __CACHE_WRITEBACK_ORDER)
-
-/*
- * There is no __cpuc_clean_dcache_area but we use it anyway for
- * code intent clarity, and alias it to __cpuc_flush_dcache_area.
- */
-#define __cpuc_clean_dcache_area __cpuc_flush_dcache_area
-
-/*
- * Ensure preceding writes to *p by this CPU are visible to
- * subsequent reads by other CPUs:
- */
-static inline void __sync_cache_range_w(volatile void *p, size_t size)
-{
- char *_p = (char *)p;
-
- __cpuc_clean_dcache_area(_p, size);
- outer_clean_range(__pa(_p), __pa(_p + size));
-}
-
-/*
- * Ensure preceding writes to *p by other CPUs are visible to
- * subsequent reads by this CPU. We must be careful not to
- * discard data simultaneously written by another CPU, hence the
- * usage of flush rather than invalidate operations.
- */
-static inline void __sync_cache_range_r(volatile void *p, size_t size)
-{
- char *_p = (char *)p;
-
-#ifdef CONFIG_OUTER_CACHE
- if (outer_cache.flush_range) {
- /*
- * Ensure dirty data migrated from other CPUs into our cache
- * are cleaned out safely before the outer cache is cleaned:
- */
- __cpuc_clean_dcache_area(_p, size);
-
- /* Clean and invalidate stale data for *p from outer ... */
- outer_flush_range(__pa(_p), __pa(_p + size));
- }
-#endif
-
- /* ... and inner cache: */
- __cpuc_flush_dcache_area(_p, size);
-}
-
-#define sync_cache_w(ptr) __sync_cache_range_w(ptr, sizeof *(ptr))
-#define sync_cache_r(ptr) __sync_cache_range_r(ptr, sizeof *(ptr))
-
#endif
diff --git a/trunk/arch/arm/include/asm/cp15.h b/trunk/arch/arm/include/asm/cp15.h
index 1f3262e99d81..5ef4d8015a60 100644
--- a/trunk/arch/arm/include/asm/cp15.h
+++ b/trunk/arch/arm/include/asm/cp15.h
@@ -42,8 +42,6 @@
#define vectors_high() (0)
#endif
-#ifdef CONFIG_CPU_CP15
-
extern unsigned long cr_no_alignment; /* defined in entry-armv.S */
extern unsigned long cr_alignment; /* defined in entry-armv.S */
@@ -84,18 +82,6 @@ static inline void set_copro_access(unsigned int val)
isb();
}
-#else /* ifdef CONFIG_CPU_CP15 */
-
-/*
- * cr_alignment and cr_no_alignment are tightly coupled to cp15 (at least in the
- * minds of the developers). Yielding 0 for machines without a cp15 (and making
- * it read-only) is fine for most cases and saves quite some #ifdeffery.
- */
-#define cr_no_alignment UL(0)
-#define cr_alignment UL(0)
-
-#endif /* ifdef CONFIG_CPU_CP15 / else */
-
-#endif /* ifndef __ASSEMBLY__ */
+#endif
#endif
diff --git a/trunk/arch/arm/include/asm/cputype.h b/trunk/arch/arm/include/asm/cputype.h
index 7652712d1d14..ad41ec2471e8 100644
--- a/trunk/arch/arm/include/asm/cputype.h
+++ b/trunk/arch/arm/include/asm/cputype.h
@@ -38,24 +38,6 @@
#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
-#define ARM_CPU_IMP_ARM 0x41
-#define ARM_CPU_IMP_INTEL 0x69
-
-#define ARM_CPU_PART_ARM1136 0xB360
-#define ARM_CPU_PART_ARM1156 0xB560
-#define ARM_CPU_PART_ARM1176 0xB760
-#define ARM_CPU_PART_ARM11MPCORE 0xB020
-#define ARM_CPU_PART_CORTEX_A8 0xC080
-#define ARM_CPU_PART_CORTEX_A9 0xC090
-#define ARM_CPU_PART_CORTEX_A5 0xC050
-#define ARM_CPU_PART_CORTEX_A15 0xC0F0
-#define ARM_CPU_PART_CORTEX_A7 0xC070
-
-#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
-#define ARM_CPU_XSCALE_ARCH_V1 0x2000
-#define ARM_CPU_XSCALE_ARCH_V2 0x4000
-#define ARM_CPU_XSCALE_ARCH_V3 0x6000
-
extern unsigned int processor_id;
#ifdef CONFIG_CPU_CP15
@@ -68,7 +50,6 @@ extern unsigned int processor_id;
: "cc"); \
__val; \
})
-
#define read_cpuid_ext(ext_reg) \
({ \
unsigned int __val; \
@@ -78,24 +59,29 @@ extern unsigned int processor_id;
: "cc"); \
__val; \
})
+#else
+#define read_cpuid(reg) (processor_id)
+#define read_cpuid_ext(reg) 0
+#endif
-#else /* ifdef CONFIG_CPU_CP15 */
-
-/*
- * read_cpuid and read_cpuid_ext should only ever be called on machines that
- * have cp15 so warn on other usages.
- */
-#define read_cpuid(reg) \
- ({ \
- WARN_ON_ONCE(1); \
- 0; \
- })
+#define ARM_CPU_IMP_ARM 0x41
+#define ARM_CPU_IMP_INTEL 0x69
-#define read_cpuid_ext(reg) read_cpuid(reg)
+#define ARM_CPU_PART_ARM1136 0xB360
+#define ARM_CPU_PART_ARM1156 0xB560
+#define ARM_CPU_PART_ARM1176 0xB760
+#define ARM_CPU_PART_ARM11MPCORE 0xB020
+#define ARM_CPU_PART_CORTEX_A8 0xC080
+#define ARM_CPU_PART_CORTEX_A9 0xC090
+#define ARM_CPU_PART_CORTEX_A5 0xC050
+#define ARM_CPU_PART_CORTEX_A15 0xC0F0
+#define ARM_CPU_PART_CORTEX_A7 0xC070
-#endif /* ifdef CONFIG_CPU_CP15 / else */
+#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
+#define ARM_CPU_XSCALE_ARCH_V1 0x2000
+#define ARM_CPU_XSCALE_ARCH_V2 0x4000
+#define ARM_CPU_XSCALE_ARCH_V3 0x6000
-#ifdef CONFIG_CPU_CP15
/*
* The CPU ID never changes at run time, so we might as well tell the
* compiler that it's constant. Use this function to read the CPU ID
@@ -106,15 +92,6 @@ static inline unsigned int __attribute_const__ read_cpuid_id(void)
return read_cpuid(CPUID_ID);
}
-#else /* ifdef CONFIG_CPU_CP15 */
-
-static inline unsigned int __attribute_const__ read_cpuid_id(void)
-{
- return processor_id;
-}
-
-#endif /* ifdef CONFIG_CPU_CP15 / else */
-
static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
{
return (read_cpuid_id() & 0xFF000000) >> 24;
diff --git a/trunk/arch/arm/include/asm/firmware.h b/trunk/arch/arm/include/asm/firmware.h
deleted file mode 100644
index 15631300c238..000000000000
--- a/trunk/arch/arm/include/asm/firmware.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics.
- * Kyungmin Park
- * Tomasz Figa
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARM_FIRMWARE_H
-#define __ASM_ARM_FIRMWARE_H
-
-#include
-
-/*
- * struct firmware_ops
- *
- * A structure to specify available firmware operations.
- *
- * A filled up structure can be registered with register_firmware_ops().
- */
-struct firmware_ops {
- /*
- * Enters CPU idle mode
- */
- int (*do_idle)(void);
- /*
- * Sets boot address of specified physical CPU
- */
- int (*set_cpu_boot_addr)(int cpu, unsigned long boot_addr);
- /*
- * Boots specified physical CPU
- */
- int (*cpu_boot)(int cpu);
- /*
- * Initializes L2 cache
- */
- int (*l2x0_init)(void);
-};
-
-/* Global pointer for current firmware_ops structure, can't be NULL. */
-extern const struct firmware_ops *firmware_ops;
-
-/*
- * call_firmware_op(op, ...)
- *
- * Checks if firmware operation is present and calls it,
- * otherwise returns -ENOSYS
- */
-#define call_firmware_op(op, ...) \
- ((firmware_ops->op) ? firmware_ops->op(__VA_ARGS__) : (-ENOSYS))
-
-/*
- * register_firmware_ops(ops)
- *
- * A function to register platform firmware_ops struct.
- */
-static inline void register_firmware_ops(const struct firmware_ops *ops)
-{
- BUG_ON(!ops);
-
- firmware_ops = ops;
-}
-
-#endif
diff --git a/trunk/arch/arm/include/asm/glue-df.h b/trunk/arch/arm/include/asm/glue-df.h
index b6e9f2c108b5..8cacbcda76da 100644
--- a/trunk/arch/arm/include/asm/glue-df.h
+++ b/trunk/arch/arm/include/asm/glue-df.h
@@ -18,12 +18,12 @@
* ================
*
* We have the following to choose from:
+ * arm6 - ARM6 style
* arm7 - ARM7 style
* v4_early - ARMv4 without Thumb early abort handler
* v4t_late - ARMv4 with Thumb late abort handler
* v4t_early - ARMv4 with Thumb early abort handler
- * v5t_early - ARMv5 with Thumb early abort handler
- * v5tj_early - ARMv5 with Thumb and Java early abort handler
+ * v5tej_early - ARMv5 with Thumb and Java early abort handler
* xscale - ARMv5 with Thumb with Xscale extensions
* v6_early - ARMv6 generic early abort handler
* v7_early - ARMv7 generic early abort handler
@@ -39,19 +39,19 @@
# endif
#endif
-#ifdef CONFIG_CPU_ABRT_EV4
+#ifdef CONFIG_CPU_ABRT_LV4T
# ifdef CPU_DABORT_HANDLER
# define MULTI_DABORT 1
# else
-# define CPU_DABORT_HANDLER v4_early_abort
+# define CPU_DABORT_HANDLER v4t_late_abort
# endif
#endif
-#ifdef CONFIG_CPU_ABRT_LV4T
+#ifdef CONFIG_CPU_ABRT_EV4
# ifdef CPU_DABORT_HANDLER
# define MULTI_DABORT 1
# else
-# define CPU_DABORT_HANDLER v4t_late_abort
+# define CPU_DABORT_HANDLER v4_early_abort
# endif
#endif
@@ -63,19 +63,19 @@
# endif
#endif
-#ifdef CONFIG_CPU_ABRT_EV5T
+#ifdef CONFIG_CPU_ABRT_EV5TJ
# ifdef CPU_DABORT_HANDLER
# define MULTI_DABORT 1
# else
-# define CPU_DABORT_HANDLER v5t_early_abort
+# define CPU_DABORT_HANDLER v5tj_early_abort
# endif
#endif
-#ifdef CONFIG_CPU_ABRT_EV5TJ
+#ifdef CONFIG_CPU_ABRT_EV5T
# ifdef CPU_DABORT_HANDLER
# define MULTI_DABORT 1
# else
-# define CPU_DABORT_HANDLER v5tj_early_abort
+# define CPU_DABORT_HANDLER v5t_early_abort
# endif
#endif
diff --git a/trunk/arch/arm/include/asm/kvm_arm.h b/trunk/arch/arm/include/asm/kvm_arm.h
index 124623e5ef14..7c3d813e15df 100644
--- a/trunk/arch/arm/include/asm/kvm_arm.h
+++ b/trunk/arch/arm/include/asm/kvm_arm.h
@@ -211,8 +211,4 @@
#define HSR_HVC_IMM_MASK ((1UL << 16) - 1)
-#define HSR_DABT_S1PTW (1U << 7)
-#define HSR_DABT_CM (1U << 8)
-#define HSR_DABT_EA (1U << 9)
-
#endif /* __ARM_KVM_ARM_H__ */
diff --git a/trunk/arch/arm/include/asm/kvm_asm.h b/trunk/arch/arm/include/asm/kvm_asm.h
index 18d50322a9e2..e4956f4e23e1 100644
--- a/trunk/arch/arm/include/asm/kvm_asm.h
+++ b/trunk/arch/arm/include/asm/kvm_asm.h
@@ -75,7 +75,7 @@ extern char __kvm_hyp_code_end[];
extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
extern void __kvm_flush_vm_context(void);
-extern void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
+extern void __kvm_tlb_flush_vmid(struct kvm *kvm);
extern int __kvm_vcpu_run(struct kvm_vcpu *vcpu);
#endif
diff --git a/trunk/arch/arm/include/asm/kvm_emulate.h b/trunk/arch/arm/include/asm/kvm_emulate.h
index 82b4babead2c..fd611996bfb5 100644
--- a/trunk/arch/arm/include/asm/kvm_emulate.h
+++ b/trunk/arch/arm/include/asm/kvm_emulate.h
@@ -22,12 +22,11 @@
#include
#include
#include
-#include
-unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
-unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu);
+u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num);
+u32 *vcpu_spsr(struct kvm_vcpu *vcpu);
-bool kvm_condition_valid(struct kvm_vcpu *vcpu);
+int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run);
void kvm_skip_instr(struct kvm_vcpu *vcpu, bool is_wide_instr);
void kvm_inject_undefined(struct kvm_vcpu *vcpu);
void kvm_inject_dabt(struct kvm_vcpu *vcpu, unsigned long addr);
@@ -38,14 +37,14 @@ static inline bool vcpu_mode_is_32bit(struct kvm_vcpu *vcpu)
return 1;
}
-static inline unsigned long *vcpu_pc(struct kvm_vcpu *vcpu)
+static inline u32 *vcpu_pc(struct kvm_vcpu *vcpu)
{
- return &vcpu->arch.regs.usr_regs.ARM_pc;
+ return (u32 *)&vcpu->arch.regs.usr_regs.ARM_pc;
}
-static inline unsigned long *vcpu_cpsr(struct kvm_vcpu *vcpu)
+static inline u32 *vcpu_cpsr(struct kvm_vcpu *vcpu)
{
- return &vcpu->arch.regs.usr_regs.ARM_cpsr;
+ return (u32 *)&vcpu->arch.regs.usr_regs.ARM_cpsr;
}
static inline void vcpu_set_thumb(struct kvm_vcpu *vcpu)
@@ -70,96 +69,4 @@ static inline bool kvm_vcpu_reg_is_pc(struct kvm_vcpu *vcpu, int reg)
return reg == 15;
}
-static inline u32 kvm_vcpu_get_hsr(struct kvm_vcpu *vcpu)
-{
- return vcpu->arch.fault.hsr;
-}
-
-static inline unsigned long kvm_vcpu_get_hfar(struct kvm_vcpu *vcpu)
-{
- return vcpu->arch.fault.hxfar;
-}
-
-static inline phys_addr_t kvm_vcpu_get_fault_ipa(struct kvm_vcpu *vcpu)
-{
- return ((phys_addr_t)vcpu->arch.fault.hpfar & HPFAR_MASK) << 8;
-}
-
-static inline unsigned long kvm_vcpu_get_hyp_pc(struct kvm_vcpu *vcpu)
-{
- return vcpu->arch.fault.hyp_pc;
-}
-
-static inline bool kvm_vcpu_dabt_isvalid(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_ISV;
-}
-
-static inline bool kvm_vcpu_dabt_iswrite(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_WNR;
-}
-
-static inline bool kvm_vcpu_dabt_issext(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_SSE;
-}
-
-static inline int kvm_vcpu_dabt_get_rd(struct kvm_vcpu *vcpu)
-{
- return (kvm_vcpu_get_hsr(vcpu) & HSR_SRT_MASK) >> HSR_SRT_SHIFT;
-}
-
-static inline bool kvm_vcpu_dabt_isextabt(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_DABT_EA;
-}
-
-static inline bool kvm_vcpu_dabt_iss1tw(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_DABT_S1PTW;
-}
-
-/* Get Access Size from a data abort */
-static inline int kvm_vcpu_dabt_get_as(struct kvm_vcpu *vcpu)
-{
- switch ((kvm_vcpu_get_hsr(vcpu) >> 22) & 0x3) {
- case 0:
- return 1;
- case 1:
- return 2;
- case 2:
- return 4;
- default:
- kvm_err("Hardware is weird: SAS 0b11 is reserved\n");
- return -EFAULT;
- }
-}
-
-/* This one is not specific to Data Abort */
-static inline bool kvm_vcpu_trap_il_is32bit(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_IL;
-}
-
-static inline u8 kvm_vcpu_trap_get_class(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) >> HSR_EC_SHIFT;
-}
-
-static inline bool kvm_vcpu_trap_is_iabt(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_trap_get_class(vcpu) == HSR_EC_IABT;
-}
-
-static inline u8 kvm_vcpu_trap_get_fault(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_FSC_TYPE;
-}
-
-static inline u32 kvm_vcpu_hvc_get_imm(struct kvm_vcpu *vcpu)
-{
- return kvm_vcpu_get_hsr(vcpu) & HSR_HVC_IMM_MASK;
-}
-
#endif /* __ARM_KVM_EMULATE_H__ */
diff --git a/trunk/arch/arm/include/asm/kvm_host.h b/trunk/arch/arm/include/asm/kvm_host.h
index 0c4e643d939e..d1736a53b12d 100644
--- a/trunk/arch/arm/include/asm/kvm_host.h
+++ b/trunk/arch/arm/include/asm/kvm_host.h
@@ -80,15 +80,6 @@ struct kvm_mmu_memory_cache {
void *objects[KVM_NR_MEM_OBJS];
};
-struct kvm_vcpu_fault_info {
- u32 hsr; /* Hyp Syndrome Register */
- u32 hxfar; /* Hyp Data/Inst. Fault Address Register */
- u32 hpfar; /* Hyp IPA Fault Address Register */
- u32 hyp_pc; /* PC when exception was taken from Hyp mode */
-};
-
-typedef struct vfp_hard_struct kvm_kernel_vfp_t;
-
struct kvm_vcpu_arch {
struct kvm_regs regs;
@@ -102,11 +93,13 @@ struct kvm_vcpu_arch {
u32 midr;
/* Exception Information */
- struct kvm_vcpu_fault_info fault;
+ u32 hsr; /* Hyp Syndrome Register */
+ u32 hxfar; /* Hyp Data/Inst Fault Address Register */
+ u32 hpfar; /* Hyp IPA Fault Address Register */
/* Floating point registers (VFP and Advanced SIMD/NEON) */
- kvm_kernel_vfp_t vfp_guest;
- kvm_kernel_vfp_t *vfp_host;
+ struct vfp_hard_struct vfp_guest;
+ struct vfp_hard_struct *vfp_host;
/* VGIC state */
struct vgic_cpu vgic_cpu;
@@ -129,6 +122,9 @@ struct kvm_vcpu_arch {
/* Interrupt related fields */
u32 irq_lines; /* IRQ and FIQ levels */
+ /* Hyp exception information */
+ u32 hyp_pc; /* PC when exception was taken from Hyp mode */
+
/* Cache some mmu pages needed inside spinlock regions */
struct kvm_mmu_memory_cache mmu_page_cache;
@@ -185,26 +181,4 @@ struct kvm_one_reg;
int kvm_arm_coproc_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
int kvm_arm_coproc_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *);
-int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
- int exception_index);
-
-static inline void __cpu_init_hyp_mode(unsigned long long pgd_ptr,
- unsigned long hyp_stack_ptr,
- unsigned long vector_ptr)
-{
- unsigned long pgd_low, pgd_high;
-
- pgd_low = (pgd_ptr & ((1ULL << 32) - 1));
- pgd_high = (pgd_ptr >> 32ULL);
-
- /*
- * Call initialization code, and switch to the full blown
- * HYP code. The init code doesn't need to preserve these registers as
- * r1-r3 and r12 are already callee save according to the AAPCS.
- * Note that we slightly misuse the prototype by casing the pgd_low to
- * a void *.
- */
- kvm_call_hyp((void *)pgd_low, pgd_high, hyp_stack_ptr, vector_ptr);
-}
-
#endif /* __ARM_KVM_HOST_H__ */
diff --git a/trunk/arch/arm/include/asm/kvm_mmu.h b/trunk/arch/arm/include/asm/kvm_mmu.h
index 970f3b5fa109..421a20b34874 100644
--- a/trunk/arch/arm/include/asm/kvm_mmu.h
+++ b/trunk/arch/arm/include/asm/kvm_mmu.h
@@ -19,18 +19,6 @@
#ifndef __ARM_KVM_MMU_H__
#define __ARM_KVM_MMU_H__
-#include
-#include
-#include
-
-/*
- * We directly use the kernel VA for the HYP, as we can directly share
- * the mapping (HTTBR "covers" TTBR1).
- */
-#define HYP_PAGE_OFFSET_MASK (~0UL)
-#define HYP_PAGE_OFFSET PAGE_OFFSET
-#define KERN_TO_HYP(kva) (kva)
-
int create_hyp_mappings(void *from, void *to);
int create_hyp_io_mappings(void *from, void *to, phys_addr_t);
void free_hyp_pmds(void);
@@ -48,16 +36,6 @@ phys_addr_t kvm_mmu_get_httbr(void);
int kvm_mmu_init(void);
void kvm_clear_hyp_idmap(void);
-static inline void kvm_set_pte(pte_t *pte, pte_t new_pte)
-{
- pte_val(*pte) = new_pte;
- /*
- * flush_pmd_entry just takes a void pointer and cleans the necessary
- * cache entries, so we can reuse the function for ptes.
- */
- flush_pmd_entry(pte);
-}
-
static inline bool kvm_is_write_fault(unsigned long hsr)
{
unsigned long hsr_ec = hsr >> HSR_EC_SHIFT;
@@ -69,49 +47,4 @@ static inline bool kvm_is_write_fault(unsigned long hsr)
return true;
}
-static inline void kvm_clean_pgd(pgd_t *pgd)
-{
- clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
-}
-
-static inline void kvm_clean_pmd_entry(pmd_t *pmd)
-{
- clean_pmd_entry(pmd);
-}
-
-static inline void kvm_clean_pte(pte_t *pte)
-{
- clean_pte_table(pte);
-}
-
-static inline void kvm_set_s2pte_writable(pte_t *pte)
-{
- pte_val(*pte) |= L_PTE_S2_RDWR;
-}
-
-struct kvm;
-
-static inline void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
-{
- /*
- * If we are going to insert an instruction page and the icache is
- * either VIPT or PIPT, there is a potential problem where the host
- * (or another VM) may have used the same page as this guest, and we
- * read incorrect data from the icache. If we're using a PIPT cache,
- * we can invalidate just that page, but if we are using a VIPT cache
- * we need to invalidate the entire icache - damn shame - as written
- * in the ARM ARM (DDI 0406C.b - Page B3-1393).
- *
- * VIVT caches are tagged using both the ASID and the VMID and doesn't
- * need any kind of flushing (DDI 0406C.b - Page B3-1392).
- */
- if (icache_is_pipt()) {
- unsigned long hva = gfn_to_hva(kvm, gfn);
- __cpuc_coherent_user_range(hva, hva + PAGE_SIZE);
- } else if (!icache_is_vivt_asid_tagged()) {
- /* any kind of VIPT cache */
- __flush_icache_all();
- }
-}
-
#endif /* __ARM_KVM_MMU_H__ */
diff --git a/trunk/arch/arm/include/asm/kvm_vgic.h b/trunk/arch/arm/include/asm/kvm_vgic.h
index 343744e4809c..ab97207d9cd3 100644
--- a/trunk/arch/arm/include/asm/kvm_vgic.h
+++ b/trunk/arch/arm/include/asm/kvm_vgic.h
@@ -21,6 +21,7 @@
#include
#include
+#include
#include
#include
#include
diff --git a/trunk/arch/arm/include/asm/mach/pci.h b/trunk/arch/arm/include/asm/mach/pci.h
index 7d2c3c843801..5cf2e979b4be 100644
--- a/trunk/arch/arm/include/asm/mach/pci.h
+++ b/trunk/arch/arm/include/asm/mach/pci.h
@@ -30,11 +30,6 @@ struct hw_pci {
void (*postinit)(void);
u8 (*swizzle)(struct pci_dev *dev, u8 *pin);
int (*map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
- resource_size_t (*align_resource)(struct pci_dev *dev,
- const struct resource *res,
- resource_size_t start,
- resource_size_t size,
- resource_size_t align);
};
/*
@@ -56,12 +51,6 @@ struct pci_sys_data {
u8 (*swizzle)(struct pci_dev *, u8 *);
/* IRQ mapping */
int (*map_irq)(const struct pci_dev *, u8, u8);
- /* Resource alignement requirements */
- resource_size_t (*align_resource)(struct pci_dev *dev,
- const struct resource *res,
- resource_size_t start,
- resource_size_t size,
- resource_size_t align);
void *private_data; /* platform controller private data */
};
diff --git a/trunk/arch/arm/include/asm/mcpm.h b/trunk/arch/arm/include/asm/mcpm.h
deleted file mode 100644
index 0f7b7620e9a5..000000000000
--- a/trunk/arch/arm/include/asm/mcpm.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * arch/arm/include/asm/mcpm.h
- *
- * Created by: Nicolas Pitre, April 2012
- * Copyright: (C) 2012-2013 Linaro Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef MCPM_H
-#define MCPM_H
-
-/*
- * Maximum number of possible clusters / CPUs per cluster.
- *
- * This should be sufficient for quite a while, while keeping the
- * (assembly) code simpler. When this starts to grow then we'll have
- * to consider dynamic allocation.
- */
-#define MAX_CPUS_PER_CLUSTER 4
-#define MAX_NR_CLUSTERS 2
-
-#ifndef __ASSEMBLY__
-
-#include
-#include
-
-/*
- * Platform specific code should use this symbol to set up secondary
- * entry location for processors to use when released from reset.
- */
-extern void mcpm_entry_point(void);
-
-/*
- * This is used to indicate where the given CPU from given cluster should
- * branch once it is ready to re-enter the kernel using ptr, or NULL if it
- * should be gated. A gated CPU is held in a WFE loop until its vector
- * becomes non NULL.
- */
-void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr);
-
-/*
- * CPU/cluster power operations API for higher subsystems to use.
- */
-
-/**
- * mcpm_cpu_power_up - make given CPU in given cluster runable
- *
- * @cpu: CPU number within given cluster
- * @cluster: cluster number for the CPU
- *
- * The identified CPU is brought out of reset. If the cluster was powered
- * down then it is brought up as well, taking care not to let the other CPUs
- * in the cluster run, and ensuring appropriate cluster setup.
- *
- * Caller must ensure the appropriate entry vector is initialized with
- * mcpm_set_entry_vector() prior to calling this.
- *
- * This must be called in a sleepable context. However, the implementation
- * is strongly encouraged to return early and let the operation happen
- * asynchronously, especially when significant delays are expected.
- *
- * If the operation cannot be performed then an error code is returned.
- */
-int mcpm_cpu_power_up(unsigned int cpu, unsigned int cluster);
-
-/**
- * mcpm_cpu_power_down - power the calling CPU down
- *
- * The calling CPU is powered down.
- *
- * If this CPU is found to be the "last man standing" in the cluster
- * then the cluster is prepared for power-down too.
- *
- * This must be called with interrupts disabled.
- *
- * This does not return. Re-entry in the kernel is expected via
- * mcpm_entry_point.
- */
-void mcpm_cpu_power_down(void);
-
-/**
- * mcpm_cpu_suspend - bring the calling CPU in a suspended state
- *
- * @expected_residency: duration in microseconds the CPU is expected
- * to remain suspended, or 0 if unknown/infinity.
- *
- * The calling CPU is suspended. The expected residency argument is used
- * as a hint by the platform specific backend to implement the appropriate
- * sleep state level according to the knowledge it has on wake-up latency
- * for the given hardware.
- *
- * If this CPU is found to be the "last man standing" in the cluster
- * then the cluster may be prepared for power-down too, if the expected
- * residency makes it worthwhile.
- *
- * This must be called with interrupts disabled.
- *
- * This does not return. Re-entry in the kernel is expected via
- * mcpm_entry_point.
- */
-void mcpm_cpu_suspend(u64 expected_residency);
-
-/**
- * mcpm_cpu_powered_up - housekeeping workafter a CPU has been powered up
- *
- * This lets the platform specific backend code perform needed housekeeping
- * work. This must be called by the newly activated CPU as soon as it is
- * fully operational in kernel space, before it enables interrupts.
- *
- * If the operation cannot be performed then an error code is returned.
- */
-int mcpm_cpu_powered_up(void);
-
-/*
- * Platform specific methods used in the implementation of the above API.
- */
-struct mcpm_platform_ops {
- int (*power_up)(unsigned int cpu, unsigned int cluster);
- void (*power_down)(void);
- void (*suspend)(u64);
- void (*powered_up)(void);
-};
-
-/**
- * mcpm_platform_register - register platform specific power methods
- *
- * @ops: mcpm_platform_ops structure to register
- *
- * An error is returned if the registration has been done previously.
- */
-int __init mcpm_platform_register(const struct mcpm_platform_ops *ops);
-
-/* Synchronisation structures for coordinating safe cluster setup/teardown: */
-
-/*
- * When modifying this structure, make sure you update the MCPM_SYNC_ defines
- * to match.
- */
-struct mcpm_sync_struct {
- /* individual CPU states */
- struct {
- s8 cpu __aligned(__CACHE_WRITEBACK_GRANULE);
- } cpus[MAX_CPUS_PER_CLUSTER];
-
- /* cluster state */
- s8 cluster __aligned(__CACHE_WRITEBACK_GRANULE);
-
- /* inbound-side state */
- s8 inbound __aligned(__CACHE_WRITEBACK_GRANULE);
-};
-
-struct sync_struct {
- struct mcpm_sync_struct clusters[MAX_NR_CLUSTERS];
-};
-
-extern unsigned long sync_phys; /* physical address of *mcpm_sync */
-
-void __mcpm_cpu_going_down(unsigned int cpu, unsigned int cluster);
-void __mcpm_cpu_down(unsigned int cpu, unsigned int cluster);
-void __mcpm_outbound_leave_critical(unsigned int cluster, int state);
-bool __mcpm_outbound_enter_critical(unsigned int this_cpu, unsigned int cluster);
-int __mcpm_cluster_state(unsigned int cluster);
-
-int __init mcpm_sync_init(
- void (*power_up_setup)(unsigned int affinity_level));
-
-void __init mcpm_smp_set_ops(void);
-
-#else
-
-/*
- * asm-offsets.h causes trouble when included in .c files, and cacheflush.h
- * cannot be included in asm files. Let's work around the conflict like this.
- */
-#include
-#define __CACHE_WRITEBACK_GRANULE CACHE_WRITEBACK_GRANULE
-
-#endif /* ! __ASSEMBLY__ */
-
-/* Definitions for mcpm_sync_struct */
-#define CPU_DOWN 0x11
-#define CPU_COMING_UP 0x12
-#define CPU_UP 0x13
-#define CPU_GOING_DOWN 0x14
-
-#define CLUSTER_DOWN 0x21
-#define CLUSTER_UP 0x22
-#define CLUSTER_GOING_DOWN 0x23
-
-#define INBOUND_NOT_COMING_UP 0x31
-#define INBOUND_COMING_UP 0x32
-
-/*
- * Offsets for the mcpm_sync_struct members, for use in asm.
- * We don't want to make them global to the kernel via asm-offsets.c.
- */
-#define MCPM_SYNC_CLUSTER_CPUS 0
-#define MCPM_SYNC_CPU_SIZE __CACHE_WRITEBACK_GRANULE
-#define MCPM_SYNC_CLUSTER_CLUSTER \
- (MCPM_SYNC_CLUSTER_CPUS + MCPM_SYNC_CPU_SIZE * MAX_CPUS_PER_CLUSTER)
-#define MCPM_SYNC_CLUSTER_INBOUND \
- (MCPM_SYNC_CLUSTER_CLUSTER + __CACHE_WRITEBACK_GRANULE)
-#define MCPM_SYNC_CLUSTER_SIZE \
- (MCPM_SYNC_CLUSTER_INBOUND + __CACHE_WRITEBACK_GRANULE)
-
-#endif
diff --git a/trunk/arch/arm/include/asm/thread_info.h b/trunk/arch/arm/include/asm/thread_info.h
index 1995d1a84060..cddda1f41f0f 100644
--- a/trunk/arch/arm/include/asm/thread_info.h
+++ b/trunk/arch/arm/include/asm/thread_info.h
@@ -152,7 +152,6 @@ extern int vfp_restore_user_hwstate(struct user_vfp __user *,
#define TIF_SYSCALL_AUDIT 9
#define TIF_SYSCALL_TRACEPOINT 10
#define TIF_SECCOMP 11 /* seccomp syscall filtering active */
-#define TIF_NOHZ 12 /* in adaptive nohz mode */
#define TIF_USING_IWMMXT 17
#define TIF_MEMDIE 18 /* is terminating due to OOM killer */
#define TIF_RESTORE_SIGMASK 20
diff --git a/trunk/arch/arm/include/asm/tlbflush.h b/trunk/arch/arm/include/asm/tlbflush.h
index a3625d141c1d..ab865e65a84c 100644
--- a/trunk/arch/arm/include/asm/tlbflush.h
+++ b/trunk/arch/arm/include/asm/tlbflush.h
@@ -166,7 +166,7 @@
# define v6wbi_always_flags (-1UL)
#endif
-#define v7wbi_tlb_flags_smp (TLB_WB | TLB_BARRIER | \
+#define v7wbi_tlb_flags_smp (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
TLB_V7_UIS_FULL | TLB_V7_UIS_PAGE | \
TLB_V7_UIS_ASID | TLB_V7_UIS_BP)
#define v7wbi_tlb_flags_up (TLB_WB | TLB_DCLEAN | TLB_BARRIER | \
diff --git a/trunk/arch/arm/include/debug/pxa.S b/trunk/arch/arm/include/debug/pxa.S
deleted file mode 100644
index e1e795aa3d7f..000000000000
--- a/trunk/arch/arm/include/debug/pxa.S
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Early serial output macro for Marvell PXA/MMP SoC
- *
- * Copyright (C) 1994-1999 Russell King
- * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * Copyright (C) 2013 Haojian Zhuang
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#if defined(CONFIG_DEBUG_PXA_UART1)
-#define PXA_UART_REG_PHYS_BASE 0x40100000
-#define PXA_UART_REG_VIRT_BASE 0xf2100000
-#elif defined(CONFIG_DEBUG_MMP_UART2)
-#define PXA_UART_REG_PHYS_BASE 0xd4017000
-#define PXA_UART_REG_VIRT_BASE 0xfe017000
-#elif defined(CONFIG_DEBUG_MMP_UART3)
-#define PXA_UART_REG_PHYS_BASE 0xd4018000
-#define PXA_UART_REG_VIRT_BASE 0xfe018000
-#else
-#error "Select uart for DEBUG_LL"
-#endif
-
- .macro addruart, rp, rv, tmp
- ldr \rp, =PXA_UART_REG_PHYS_BASE
- ldr \rv, =PXA_UART_REG_VIRT_BASE
- .endm
-
-#define UART_SHIFT 2
-#include
diff --git a/trunk/arch/arm/include/debug/uncompress.h b/trunk/arch/arm/include/debug/uncompress.h
deleted file mode 100644
index 0e2949b0fae9..000000000000
--- a/trunk/arch/arm/include/debug/uncompress.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifdef CONFIG_DEBUG_UNCOMPRESS
-extern void putc(int c);
-#else
-static inline void putc(int c) {}
-#endif
-static inline void flush(void) {}
-static inline void arch_decomp_setup(void) {}
diff --git a/trunk/arch/arm/include/uapi/asm/kvm.h b/trunk/arch/arm/include/uapi/asm/kvm.h
index c1ee007523d7..023bfeb367bf 100644
--- a/trunk/arch/arm/include/uapi/asm/kvm.h
+++ b/trunk/arch/arm/include/uapi/asm/kvm.h
@@ -53,12 +53,12 @@
#define KVM_ARM_FIQ_spsr fiq_regs[7]
struct kvm_regs {
- struct pt_regs usr_regs; /* R0_usr - R14_usr, PC, CPSR */
- unsigned long svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
- unsigned long abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
- unsigned long und_regs[3]; /* SP_und, LR_und, SPSR_und */
- unsigned long irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
- unsigned long fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
+ struct pt_regs usr_regs;/* R0_usr - R14_usr, PC, CPSR */
+ __u32 svc_regs[3]; /* SP_svc, LR_svc, SPSR_svc */
+ __u32 abt_regs[3]; /* SP_abt, LR_abt, SPSR_abt */
+ __u32 und_regs[3]; /* SP_und, LR_und, SPSR_und */
+ __u32 irq_regs[3]; /* SP_irq, LR_irq, SPSR_irq */
+ __u32 fiq_regs[8]; /* R8_fiq - R14_fiq, SPSR_fiq */
};
/* Supported Processor Types */
diff --git a/trunk/arch/arm/kernel/asm-offsets.c b/trunk/arch/arm/kernel/asm-offsets.c
index a53efa993690..923eec7105cf 100644
--- a/trunk/arch/arm/kernel/asm-offsets.c
+++ b/trunk/arch/arm/kernel/asm-offsets.c
@@ -149,10 +149,6 @@ int main(void)
DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
- BLANK();
- DEFINE(CACHE_WRITEBACK_ORDER, __CACHE_WRITEBACK_ORDER);
- DEFINE(CACHE_WRITEBACK_GRANULE, __CACHE_WRITEBACK_GRANULE);
- BLANK();
#ifdef CONFIG_KVM_ARM_HOST
DEFINE(VCPU_KVM, offsetof(struct kvm_vcpu, kvm));
DEFINE(VCPU_MIDR, offsetof(struct kvm_vcpu, arch.midr));
@@ -169,10 +165,10 @@ int main(void)
DEFINE(VCPU_PC, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_pc));
DEFINE(VCPU_CPSR, offsetof(struct kvm_vcpu, arch.regs.usr_regs.ARM_cpsr));
DEFINE(VCPU_IRQ_LINES, offsetof(struct kvm_vcpu, arch.irq_lines));
- DEFINE(VCPU_HSR, offsetof(struct kvm_vcpu, arch.fault.hsr));
- DEFINE(VCPU_HxFAR, offsetof(struct kvm_vcpu, arch.fault.hxfar));
- DEFINE(VCPU_HPFAR, offsetof(struct kvm_vcpu, arch.fault.hpfar));
- DEFINE(VCPU_HYP_PC, offsetof(struct kvm_vcpu, arch.fault.hyp_pc));
+ DEFINE(VCPU_HSR, offsetof(struct kvm_vcpu, arch.hsr));
+ DEFINE(VCPU_HxFAR, offsetof(struct kvm_vcpu, arch.hxfar));
+ DEFINE(VCPU_HPFAR, offsetof(struct kvm_vcpu, arch.hpfar));
+ DEFINE(VCPU_HYP_PC, offsetof(struct kvm_vcpu, arch.hyp_pc));
#ifdef CONFIG_KVM_ARM_VGIC
DEFINE(VCPU_VGIC_CPU, offsetof(struct kvm_vcpu, arch.vgic_cpu));
DEFINE(VGIC_CPU_HCR, offsetof(struct vgic_cpu, vgic_hcr));
diff --git a/trunk/arch/arm/kernel/bios32.c b/trunk/arch/arm/kernel/bios32.c
index b2ed73c45489..a1f73b502ef0 100644
--- a/trunk/arch/arm/kernel/bios32.c
+++ b/trunk/arch/arm/kernel/bios32.c
@@ -462,7 +462,6 @@ static void pcibios_init_hw(struct hw_pci *hw, struct list_head *head)
sys->busnr = busnr;
sys->swizzle = hw->swizzle;
sys->map_irq = hw->map_irq;
- sys->align_resource = hw->align_resource;
INIT_LIST_HEAD(&sys->resources);
if (hw->private_data)
@@ -575,8 +574,6 @@ char * __init pcibios_setup(char *str)
resource_size_t pcibios_align_resource(void *data, const struct resource *res,
resource_size_t size, resource_size_t align)
{
- struct pci_dev *dev = data;
- struct pci_sys_data *sys = dev->sysdata;
resource_size_t start = res->start;
if (res->flags & IORESOURCE_IO && start & 0x300)
@@ -584,9 +581,6 @@ resource_size_t pcibios_align_resource(void *data, const struct resource *res,
start = (start + align - 1) & ~(align - 1);
- if (sys->align_resource)
- return sys->align_resource(dev, res, start, size, align);
-
return start;
}
diff --git a/trunk/arch/arm/kernel/entry-armv.S b/trunk/arch/arm/kernel/entry-armv.S
index 582b405befc5..0f82098c9bfe 100644
--- a/trunk/arch/arm/kernel/entry-armv.S
+++ b/trunk/arch/arm/kernel/entry-armv.S
@@ -192,6 +192,18 @@ __dabt_svc:
svc_entry
mov r2, sp
dabt_helper
+
+ @
+ @ IRQs off again before pulling preserved data off the stack
+ @
+ disable_irq_notrace
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+ tst r5, #PSR_I_BIT
+ bleq trace_hardirqs_on
+ tst r5, #PSR_I_BIT
+ blne trace_hardirqs_off
+#endif
svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__dabt_svc)
@@ -211,7 +223,12 @@ __irq_svc:
blne svc_preempt
#endif
- svc_exit r5, irq = 1 @ return from exception
+#ifdef CONFIG_TRACE_IRQFLAGS
+ @ The parent context IRQs must have been enabled to get here in
+ @ the first place, so there's no point checking the PSR I bit.
+ bl trace_hardirqs_on
+#endif
+ svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__irq_svc)
@@ -278,8 +295,22 @@ __und_svc_fault:
mov r0, sp @ struct pt_regs *regs
bl __und_fault
+ @
+ @ IRQs off again before pulling preserved data off the stack
+ @
__und_svc_finish:
+ disable_irq_notrace
+
+ @
+ @ restore SPSR and restart the instruction
+ @
ldr r5, [sp, #S_PSR] @ Get SVC cpsr
+#ifdef CONFIG_TRACE_IRQFLAGS
+ tst r5, #PSR_I_BIT
+ bleq trace_hardirqs_on
+ tst r5, #PSR_I_BIT
+ blne trace_hardirqs_off
+#endif
svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__und_svc)
@@ -289,6 +320,18 @@ __pabt_svc:
svc_entry
mov r2, sp @ regs
pabt_helper
+
+ @
+ @ IRQs off again before pulling preserved data off the stack
+ @
+ disable_irq_notrace
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+ tst r5, #PSR_I_BIT
+ bleq trace_hardirqs_on
+ tst r5, #PSR_I_BIT
+ blne trace_hardirqs_off
+#endif
svc_exit r5 @ return from exception
UNWIND(.fnend )
ENDPROC(__pabt_svc)
@@ -353,7 +396,6 @@ ENDPROC(__pabt_svc)
#ifdef CONFIG_IRQSOFF_TRACER
bl trace_hardirqs_off
#endif
- ct_user_exit save = 0
.endm
.macro kuser_cmpxchg_check
@@ -520,21 +562,21 @@ ENDPROC(__und_usr)
@ Fall-through from Thumb-2 __und_usr
@
#ifdef CONFIG_NEON
- get_thread_info r10 @ get current thread
adr r6, .LCneon_thumb_opcodes
b 2f
#endif
call_fpe:
- get_thread_info r10 @ get current thread
#ifdef CONFIG_NEON
adr r6, .LCneon_arm_opcodes
-2: ldr r5, [r6], #4 @ mask value
- ldr r7, [r6], #4 @ opcode bits matching in mask
- cmp r5, #0 @ end mask?
+2:
+ ldr r7, [r6], #4 @ mask value
+ cmp r7, #0 @ end mask?
beq 1f
- and r8, r0, r5
+ and r8, r0, r7
+ ldr r7, [r6], #4 @ opcode bits matching in mask
cmp r8, r7 @ NEON instruction?
bne 2b
+ get_thread_info r10
mov r7, #1
strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
@@ -544,6 +586,7 @@ call_fpe:
tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
moveq pc, lr
+ get_thread_info r10 @ get current thread
and r8, r0, #0x00000f00 @ mask out CP number
THUMB( lsr r8, r8, #8 )
mov r7, #1
diff --git a/trunk/arch/arm/kernel/entry-common.S b/trunk/arch/arm/kernel/entry-common.S
index bc5bc0a97131..fefd7f971437 100644
--- a/trunk/arch/arm/kernel/entry-common.S
+++ b/trunk/arch/arm/kernel/entry-common.S
@@ -35,11 +35,12 @@ ret_fast_syscall:
ldr r1, [tsk, #TI_FLAGS]
tst r1, #_TIF_WORK_MASK
bne fast_work_pending
+#if defined(CONFIG_IRQSOFF_TRACER)
asm_trace_hardirqs_on
+#endif
/* perform architecture specific actions before user return */
arch_ret_to_user r1, lr
- ct_user_enter
restore_user_regs fast = 1, offset = S_OFF
UNWIND(.fnend )
@@ -70,11 +71,11 @@ ENTRY(ret_to_user_from_irq)
tst r1, #_TIF_WORK_MASK
bne work_pending
no_work_pending:
+#if defined(CONFIG_IRQSOFF_TRACER)
asm_trace_hardirqs_on
-
+#endif
/* perform architecture specific actions before user return */
arch_ret_to_user r1, lr
- ct_user_enter save = 0
restore_user_regs fast = 0, offset = 0
ENDPROC(ret_to_user_from_irq)
@@ -405,7 +406,6 @@ ENTRY(vector_swi)
mcr p15, 0, ip, c1, c0 @ update control register
#endif
enable_irq
- ct_user_exit
get_thread_info tsk
adr tbl, sys_call_table @ load syscall table pointer
diff --git a/trunk/arch/arm/kernel/entry-header.S b/trunk/arch/arm/kernel/entry-header.S
index 160f3376ba6d..9a8531eadd3d 100644
--- a/trunk/arch/arm/kernel/entry-header.S
+++ b/trunk/arch/arm/kernel/entry-header.S
@@ -74,24 +74,7 @@
.endm
#ifndef CONFIG_THUMB2_KERNEL
- .macro svc_exit, rpsr, irq = 0
- .if \irq != 0
- @ IRQs already off
-#ifdef CONFIG_TRACE_IRQFLAGS
- @ The parent context IRQs must have been enabled to get here in
- @ the first place, so there's no point checking the PSR I bit.
- bl trace_hardirqs_on
-#endif
- .else
- @ IRQs off again before pulling preserved data off the stack
- disable_irq_notrace
-#ifdef CONFIG_TRACE_IRQFLAGS
- tst \rpsr, #PSR_I_BIT
- bleq trace_hardirqs_on
- tst \rpsr, #PSR_I_BIT
- blne trace_hardirqs_off
-#endif
- .endif
+ .macro svc_exit, rpsr
msr spsr_cxsf, \rpsr
#if defined(CONFIG_CPU_V6)
ldr r0, [sp]
@@ -137,24 +120,7 @@
mov pc, \reg
.endm
#else /* CONFIG_THUMB2_KERNEL */
- .macro svc_exit, rpsr, irq = 0
- .if \irq != 0
- @ IRQs already off
-#ifdef CONFIG_TRACE_IRQFLAGS
- @ The parent context IRQs must have been enabled to get here in
- @ the first place, so there's no point checking the PSR I bit.
- bl trace_hardirqs_on
-#endif
- .else
- @ IRQs off again before pulling preserved data off the stack
- disable_irq_notrace
-#ifdef CONFIG_TRACE_IRQFLAGS
- tst \rpsr, #PSR_I_BIT
- bleq trace_hardirqs_on
- tst \rpsr, #PSR_I_BIT
- blne trace_hardirqs_off
-#endif
- .endif
+ .macro svc_exit, rpsr
ldr lr, [sp, #S_SP] @ top of the stack
ldrd r0, r1, [sp, #S_LR] @ calling lr and pc
clrex @ clear the exclusive monitor
@@ -197,34 +163,6 @@
.endm
#endif /* !CONFIG_THUMB2_KERNEL */
-/*
- * Context tracking subsystem. Used to instrument transitions
- * between user and kernel mode.
- */
- .macro ct_user_exit, save = 1
-#ifdef CONFIG_CONTEXT_TRACKING
- .if \save
- stmdb sp!, {r0-r3, ip, lr}
- bl user_exit
- ldmia sp!, {r0-r3, ip, lr}
- .else
- bl user_exit
- .endif
-#endif
- .endm
-
- .macro ct_user_enter, save = 1
-#ifdef CONFIG_CONTEXT_TRACKING
- .if \save
- stmdb sp!, {r0-r3, ip, lr}
- bl user_enter
- ldmia sp!, {r0-r3, ip, lr}
- .else
- bl user_enter
- .endif
-#endif
- .endm
-
/*
* These are the registers used in the syscall handler, and allow us to
* have in theory up to 7 arguments to a function - r0 to r6.
diff --git a/trunk/arch/arm/kernel/head-common.S b/trunk/arch/arm/kernel/head-common.S
index 5b391a689b47..854bd22380d3 100644
--- a/trunk/arch/arm/kernel/head-common.S
+++ b/trunk/arch/arm/kernel/head-common.S
@@ -98,9 +98,8 @@ __mmap_switched:
str r9, [r4] @ Save processor ID
str r1, [r5] @ Save machine type
str r2, [r6] @ Save atags pointer
- cmp r7, #0
- bicne r4, r0, #CR_A @ Clear 'A' bit
- stmneia r7, {r0, r4} @ Save control register values
+ bic r4, r0, #CR_A @ Clear 'A' bit
+ stmia r7, {r0, r4} @ Save control register values
b start_kernel
ENDPROC(__mmap_switched)
@@ -114,11 +113,7 @@ __mmap_switched_data:
.long processor_id @ r4
.long __machine_arch_type @ r5
.long __atags_pointer @ r6
-#ifdef CONFIG_CPU_CP15
.long cr_alignment @ r7
-#else
- .long 0 @ r7
-#endif
.long init_thread_union + THREAD_START_SP @ sp
.size __mmap_switched_data, . - __mmap_switched_data
diff --git a/trunk/arch/arm/kernel/head-nommu.S b/trunk/arch/arm/kernel/head-nommu.S
index 6a2e09c952c7..2c228a07e58c 100644
--- a/trunk/arch/arm/kernel/head-nommu.S
+++ b/trunk/arch/arm/kernel/head-nommu.S
@@ -32,21 +32,15 @@
* numbers for r1.
*
*/
+ .arm
__HEAD
-
-#ifdef CONFIG_CPU_THUMBONLY
- .thumb
-ENTRY(stext)
-#else
- .arm
ENTRY(stext)
THUMB( adr r9, BSYM(1f) ) @ Kernel is always entered in ARM.
THUMB( bx r9 ) @ If this is a Thumb-2 kernel,
THUMB( .thumb ) @ switch to Thumb now.
THUMB(1: )
-#endif
setmode PSR_F_BIT | PSR_I_BIT | SVC_MODE, r9 @ ensure svc mode
@ and irqs disabled
diff --git a/trunk/arch/arm/kernel/process.c b/trunk/arch/arm/kernel/process.c
index f21970316836..ae58d3b37d9d 100644
--- a/trunk/arch/arm/kernel/process.c
+++ b/trunk/arch/arm/kernel/process.c
@@ -407,16 +407,15 @@ unsigned long arch_randomize_brk(struct mm_struct *mm)
* atomic helpers and the signal restart code. Insert it into the
* gate_vma so that it is visible through ptrace and /proc//mem.
*/
-static struct vm_area_struct gate_vma = {
- .vm_start = 0xffff0000,
- .vm_end = 0xffff0000 + PAGE_SIZE,
- .vm_flags = VM_READ | VM_EXEC | VM_MAYREAD | VM_MAYEXEC,
- .vm_mm = &init_mm,
-};
+static struct vm_area_struct gate_vma;
static int __init gate_vma_init(void)
{
- gate_vma.vm_page_prot = PAGE_READONLY_EXEC;
+ gate_vma.vm_start = 0xffff0000;
+ gate_vma.vm_end = 0xffff0000 + PAGE_SIZE;
+ gate_vma.vm_page_prot = PAGE_READONLY_EXEC;
+ gate_vma.vm_flags = VM_READ | VM_EXEC |
+ VM_MAYREAD | VM_MAYEXEC;
return 0;
}
arch_initcall(gate_vma_init);
diff --git a/trunk/arch/arm/kernel/return_address.c b/trunk/arch/arm/kernel/return_address.c
index fafedd86885d..8085417555dd 100644
--- a/trunk/arch/arm/kernel/return_address.c
+++ b/trunk/arch/arm/kernel/return_address.c
@@ -26,7 +26,7 @@ static int save_return_addr(struct stackframe *frame, void *d)
struct return_address_data *data = d;
if (!data->level) {
- data->addr = (void *)frame->pc;
+ data->addr = (void *)frame->lr;
return 1;
} else {
@@ -41,8 +41,7 @@ void *return_address(unsigned int level)
struct stackframe frame;
register unsigned long current_sp asm ("sp");
- data.level = level + 2;
- data.addr = NULL;
+ data.level = level + 1;
frame.fp = (unsigned long)__builtin_frame_address(0);
frame.sp = current_sp;
diff --git a/trunk/arch/arm/kernel/setup.c b/trunk/arch/arm/kernel/setup.c
index 728007c4a2b7..234e339196c0 100644
--- a/trunk/arch/arm/kernel/setup.c
+++ b/trunk/arch/arm/kernel/setup.c
@@ -290,10 +290,10 @@ static int cpu_has_aliasing_icache(unsigned int arch)
static void __init cacheid_init(void)
{
+ unsigned int cachetype = read_cpuid_cachetype();
unsigned int arch = cpu_architecture();
if (arch >= CPU_ARCH_ARMv6) {
- unsigned int cachetype = read_cpuid_cachetype();
if ((cachetype & (7 << 29)) == 4 << 29) {
/* ARMv7 register format */
arch = CPU_ARCH_ARMv7;
@@ -389,7 +389,7 @@ static void __init feat_v6_fixup(void)
*
* cpu_init sets up the per-CPU stacks.
*/
-void notrace cpu_init(void)
+void cpu_init(void)
{
unsigned int cpu = smp_processor_id();
struct stack *stk = &stacks[cpu];
diff --git a/trunk/arch/arm/kernel/smp.c b/trunk/arch/arm/kernel/smp.c
index 47ab90563bf4..4619177bcfe6 100644
--- a/trunk/arch/arm/kernel/smp.c
+++ b/trunk/arch/arm/kernel/smp.c
@@ -211,13 +211,6 @@ void __cpuinit __cpu_die(unsigned int cpu)
}
printk(KERN_NOTICE "CPU%u: shutdown\n", cpu);
- /*
- * platform_cpu_kill() is generally expected to do the powering off
- * and/or cutting of clocks to the dying CPU. Optionally, this may
- * be done by the CPU which is dying in preference to supporting
- * this call, but that means there is _no_ synchronisation between
- * the requesting CPU and the dying CPU actually losing power.
- */
if (!platform_cpu_kill(cpu))
printk("CPU%u: unable to kill\n", cpu);
}
@@ -237,41 +230,14 @@ void __ref cpu_die(void)
idle_task_exit();
local_irq_disable();
+ mb();
- /*
- * Flush the data out of the L1 cache for this CPU. This must be
- * before the completion to ensure that data is safely written out
- * before platform_cpu_kill() gets called - which may disable
- * *this* CPU and power down its cache.
- */
- flush_cache_louis();
-
- /*
- * Tell __cpu_die() that this CPU is now safe to dispose of. Once
- * this returns, power and/or clocks can be removed at any point
- * from this CPU and its cache by platform_cpu_kill().
- */
+ /* Tell __cpu_die() that this CPU is now safe to dispose of */
RCU_NONIDLE(complete(&cpu_died));
/*
- * Ensure that the cache lines associated with that completion are
- * written out. This covers the case where _this_ CPU is doing the
- * powering down, to ensure that the completion is visible to the
- * CPU waiting for this one.
- */
- flush_cache_louis();
-
- /*
- * The actual CPU shutdown procedure is at least platform (if not
- * CPU) specific. This may remove power, or it may simply spin.
- *
- * Platforms are generally expected *NOT* to return from this call,
- * although there are some which do because they have no way to
- * power down the CPU. These platforms are the _only_ reason we
- * have a return path which uses the fragment of assembly below.
- *
- * The return path should not be used for platforms which can
- * power off the CPU.
+ * actual CPU shutdown procedure is at least platform (if not
+ * CPU) specific.
*/
if (smp_ops.cpu_die)
smp_ops.cpu_die(cpu);
diff --git a/trunk/arch/arm/kernel/smp_scu.c b/trunk/arch/arm/kernel/smp_scu.c
index 5bc1a63284e3..45eac87ed66a 100644
--- a/trunk/arch/arm/kernel/smp_scu.c
+++ b/trunk/arch/arm/kernel/smp_scu.c
@@ -41,7 +41,7 @@ void scu_enable(void __iomem *scu_base)
#ifdef CONFIG_ARM_ERRATA_764369
/* Cortex-A9 only */
- if ((read_cpuid_id() & 0xff0ffff0) == 0x410fc090) {
+ if ((read_cpuid(CPUID_ID) & 0xff0ffff0) == 0x410fc090) {
scu_ctrl = __raw_readl(scu_base + 0x30);
if (!(scu_ctrl & 1))
__raw_writel(scu_ctrl | 0x1, scu_base + 0x30);
diff --git a/trunk/arch/arm/kernel/smp_tlb.c b/trunk/arch/arm/kernel/smp_tlb.c
index 9a52a07aa40e..e82e1d248772 100644
--- a/trunk/arch/arm/kernel/smp_tlb.c
+++ b/trunk/arch/arm/kernel/smp_tlb.c
@@ -98,21 +98,21 @@ static void broadcast_tlb_a15_erratum(void)
return;
dummy_flush_tlb_a15_erratum();
- smp_call_function(ipi_flush_tlb_a15_erratum, NULL, 1);
+ smp_call_function_many(cpu_online_mask, ipi_flush_tlb_a15_erratum,
+ NULL, 1);
}
static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
{
- int cpu, this_cpu;
+ int cpu;
cpumask_t mask = { CPU_BITS_NONE };
if (!erratum_a15_798181())
return;
dummy_flush_tlb_a15_erratum();
- this_cpu = get_cpu();
for_each_online_cpu(cpu) {
- if (cpu == this_cpu)
+ if (cpu == smp_processor_id())
continue;
/*
* We only need to send an IPI if the other CPUs are running
@@ -127,7 +127,6 @@ static void broadcast_tlb_mm_a15_erratum(struct mm_struct *mm)
cpumask_set_cpu(cpu, &mask);
}
smp_call_function_many(&mask, ipi_flush_tlb_a15_erratum, NULL, 1);
- put_cpu();
}
void flush_tlb_all(void)
diff --git a/trunk/arch/arm/kvm/Makefile b/trunk/arch/arm/kvm/Makefile
index 8dc5e76cb789..fc96ce6f2357 100644
--- a/trunk/arch/arm/kvm/Makefile
+++ b/trunk/arch/arm/kvm/Makefile
@@ -17,7 +17,7 @@ AFLAGS_interrupts.o := -Wa,-march=armv7-a$(plus_virt)
kvm-arm-y = $(addprefix ../../../virt/kvm/, kvm_main.o coalesced_mmio.o)
obj-y += kvm-arm.o init.o interrupts.o
-obj-y += arm.o handle_exit.o guest.o mmu.o emulate.o reset.o
+obj-y += arm.o guest.o mmu.o emulate.o reset.o
obj-y += coproc.o coproc_a15.o mmio.o psci.o
obj-$(CONFIG_KVM_ARM_VGIC) += vgic.o
obj-$(CONFIG_KVM_ARM_TIMER) += arch_timer.o
diff --git a/trunk/arch/arm/kvm/arm.c b/trunk/arch/arm/kvm/arm.c
index a0dfc2a53f91..842098d78f58 100644
--- a/trunk/arch/arm/kvm/arm.c
+++ b/trunk/arch/arm/kvm/arm.c
@@ -30,9 +30,11 @@
#define CREATE_TRACE_POINTS
#include "trace.h"
+#include
#include
#include
#include
+#include
#include
#include
#include
@@ -42,13 +44,14 @@
#include
#include
#include
+#include
#ifdef REQUIRES_VIRT
__asm__(".arch_extension virt");
#endif
static DEFINE_PER_CPU(unsigned long, kvm_arm_hyp_stack_page);
-static kvm_kernel_vfp_t __percpu *kvm_host_vfp_state;
+static struct vfp_hard_struct __percpu *kvm_host_vfp_state;
static unsigned long hyp_default_vectors;
/* Per-CPU variable containing the currently running vcpu. */
@@ -301,6 +304,22 @@ int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu)
return 0;
}
+int __attribute_const__ kvm_target_cpu(void)
+{
+ unsigned long implementor = read_cpuid_implementor();
+ unsigned long part_number = read_cpuid_part_number();
+
+ if (implementor != ARM_CPU_IMP_ARM)
+ return -EINVAL;
+
+ switch (part_number) {
+ case ARM_CPU_PART_CORTEX_A15:
+ return KVM_ARM_TARGET_CORTEX_A15;
+ default:
+ return -EINVAL;
+ }
+}
+
int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
{
int ret;
@@ -463,6 +482,163 @@ static void update_vttbr(struct kvm *kvm)
spin_unlock(&kvm_vmid_lock);
}
+static int handle_svc_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+ /* SVC called from Hyp mode should never get here */
+ kvm_debug("SVC called from Hyp mode shouldn't go here\n");
+ BUG();
+ return -EINVAL; /* Squash warning */
+}
+
+static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+ trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0),
+ vcpu->arch.hsr & HSR_HVC_IMM_MASK);
+
+ if (kvm_psci_call(vcpu))
+ return 1;
+
+ kvm_inject_undefined(vcpu);
+ return 1;
+}
+
+static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+ if (kvm_psci_call(vcpu))
+ return 1;
+
+ kvm_inject_undefined(vcpu);
+ return 1;
+}
+
+static int handle_pabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+ /* The hypervisor should never cause aborts */
+ kvm_err("Prefetch Abort taken from Hyp mode at %#08x (HSR: %#08x)\n",
+ vcpu->arch.hxfar, vcpu->arch.hsr);
+ return -EFAULT;
+}
+
+static int handle_dabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
+{
+ /* This is either an error in the ws. code or an external abort */
+ kvm_err("Data Abort taken from Hyp mode at %#08x (HSR: %#08x)\n",
+ vcpu->arch.hxfar, vcpu->arch.hsr);
+ return -EFAULT;
+}
+
+typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
+static exit_handle_fn arm_exit_handlers[] = {
+ [HSR_EC_WFI] = kvm_handle_wfi,
+ [HSR_EC_CP15_32] = kvm_handle_cp15_32,
+ [HSR_EC_CP15_64] = kvm_handle_cp15_64,
+ [HSR_EC_CP14_MR] = kvm_handle_cp14_access,
+ [HSR_EC_CP14_LS] = kvm_handle_cp14_load_store,
+ [HSR_EC_CP14_64] = kvm_handle_cp14_access,
+ [HSR_EC_CP_0_13] = kvm_handle_cp_0_13_access,
+ [HSR_EC_CP10_ID] = kvm_handle_cp10_id,
+ [HSR_EC_SVC_HYP] = handle_svc_hyp,
+ [HSR_EC_HVC] = handle_hvc,
+ [HSR_EC_SMC] = handle_smc,
+ [HSR_EC_IABT] = kvm_handle_guest_abort,
+ [HSR_EC_IABT_HYP] = handle_pabt_hyp,
+ [HSR_EC_DABT] = kvm_handle_guest_abort,
+ [HSR_EC_DABT_HYP] = handle_dabt_hyp,
+};
+
+/*
+ * A conditional instruction is allowed to trap, even though it
+ * wouldn't be executed. So let's re-implement the hardware, in
+ * software!
+ */
+static bool kvm_condition_valid(struct kvm_vcpu *vcpu)
+{
+ unsigned long cpsr, cond, insn;
+
+ /*
+ * Exception Code 0 can only happen if we set HCR.TGE to 1, to
+ * catch undefined instructions, and then we won't get past
+ * the arm_exit_handlers test anyway.
+ */
+ BUG_ON(((vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT) == 0);
+
+ /* Top two bits non-zero? Unconditional. */
+ if (vcpu->arch.hsr >> 30)
+ return true;
+
+ cpsr = *vcpu_cpsr(vcpu);
+
+ /* Is condition field valid? */
+ if ((vcpu->arch.hsr & HSR_CV) >> HSR_CV_SHIFT)
+ cond = (vcpu->arch.hsr & HSR_COND) >> HSR_COND_SHIFT;
+ else {
+ /* This can happen in Thumb mode: examine IT state. */
+ unsigned long it;
+
+ it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
+
+ /* it == 0 => unconditional. */
+ if (it == 0)
+ return true;
+
+ /* The cond for this insn works out as the top 4 bits. */
+ cond = (it >> 4);
+ }
+
+ /* Shift makes it look like an ARM-mode instruction */
+ insn = cond << 28;
+ return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL;
+}
+
+/*
+ * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
+ * proper exit to QEMU.
+ */
+static int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
+ int exception_index)
+{
+ unsigned long hsr_ec;
+
+ switch (exception_index) {
+ case ARM_EXCEPTION_IRQ:
+ return 1;
+ case ARM_EXCEPTION_UNDEFINED:
+ kvm_err("Undefined exception in Hyp mode at: %#08x\n",
+ vcpu->arch.hyp_pc);
+ BUG();
+ panic("KVM: Hypervisor undefined exception!\n");
+ case ARM_EXCEPTION_DATA_ABORT:
+ case ARM_EXCEPTION_PREF_ABORT:
+ case ARM_EXCEPTION_HVC:
+ hsr_ec = (vcpu->arch.hsr & HSR_EC) >> HSR_EC_SHIFT;
+
+ if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers)
+ || !arm_exit_handlers[hsr_ec]) {
+ kvm_err("Unknown exception class: %#08lx, "
+ "hsr: %#08x\n", hsr_ec,
+ (unsigned int)vcpu->arch.hsr);
+ BUG();
+ }
+
+ /*
+ * See ARM ARM B1.14.1: "Hyp traps on instructions
+ * that fail their condition code check"
+ */
+ if (!kvm_condition_valid(vcpu)) {
+ bool is_wide = vcpu->arch.hsr & HSR_IL;
+ kvm_skip_instr(vcpu, is_wide);
+ return 1;
+ }
+
+ return arm_exit_handlers[hsr_ec](vcpu, run);
+ default:
+ kvm_pr_unimpl("Unsupported exception type: %d",
+ exception_index);
+ run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
+ return 0;
+ }
+}
+
static int kvm_vcpu_first_run_init(struct kvm_vcpu *vcpu)
{
if (likely(vcpu->arch.has_run_once))
@@ -797,6 +973,7 @@ long kvm_arch_vm_ioctl(struct file *filp,
static void cpu_init_hyp_mode(void *vector)
{
unsigned long long pgd_ptr;
+ unsigned long pgd_low, pgd_high;
unsigned long hyp_stack_ptr;
unsigned long stack_page;
unsigned long vector_ptr;
@@ -805,11 +982,20 @@ static void cpu_init_hyp_mode(void *vector)
__hyp_set_vectors((unsigned long)vector);
pgd_ptr = (unsigned long long)kvm_mmu_get_httbr();
+ pgd_low = (pgd_ptr & ((1ULL << 32) - 1));
+ pgd_high = (pgd_ptr >> 32ULL);
stack_page = __get_cpu_var(kvm_arm_hyp_stack_page);
hyp_stack_ptr = stack_page + PAGE_SIZE;
vector_ptr = (unsigned long)__kvm_hyp_vector;
- __cpu_init_hyp_mode(pgd_ptr, hyp_stack_ptr, vector_ptr);
+ /*
+ * Call initialization code, and switch to the full blown
+ * HYP code. The init code doesn't need to preserve these registers as
+ * r1-r3 and r12 are already callee save according to the AAPCS.
+ * Note that we slightly misuse the prototype by casing the pgd_low to
+ * a void *.
+ */
+ kvm_call_hyp((void *)pgd_low, pgd_high, hyp_stack_ptr, vector_ptr);
}
/**
@@ -892,7 +1078,7 @@ static int init_hyp_mode(void)
/*
* Map the host VFP structures
*/
- kvm_host_vfp_state = alloc_percpu(kvm_kernel_vfp_t);
+ kvm_host_vfp_state = alloc_percpu(struct vfp_hard_struct);
if (!kvm_host_vfp_state) {
err = -ENOMEM;
kvm_err("Cannot allocate host VFP state\n");
@@ -900,7 +1086,7 @@ static int init_hyp_mode(void)
}
for_each_possible_cpu(cpu) {
- kvm_kernel_vfp_t *vfp;
+ struct vfp_hard_struct *vfp;
vfp = per_cpu_ptr(kvm_host_vfp_state, cpu);
err = create_hyp_mappings(vfp, vfp + 1);
diff --git a/trunk/arch/arm/kvm/coproc.c b/trunk/arch/arm/kvm/coproc.c
index 8eea97be1ed5..7bed7556077a 100644
--- a/trunk/arch/arm/kvm/coproc.c
+++ b/trunk/arch/arm/kvm/coproc.c
@@ -76,7 +76,7 @@ static bool access_dcsw(struct kvm_vcpu *vcpu,
const struct coproc_params *p,
const struct coproc_reg *r)
{
- unsigned long val;
+ u32 val;
int cpu;
if (!p->is_write)
@@ -293,12 +293,12 @@ static int emulate_cp15(struct kvm_vcpu *vcpu,
if (likely(r->access(vcpu, params, r))) {
/* Skip instruction, since it was emulated */
- kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+ kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1);
return 1;
}
/* If access function fails, it should complain. */
} else {
- kvm_err("Unsupported guest CP15 access at: %08lx\n",
+ kvm_err("Unsupported guest CP15 access at: %08x\n",
*vcpu_pc(vcpu));
print_cp_instr(params);
}
@@ -315,14 +315,14 @@ int kvm_handle_cp15_64(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
struct coproc_params params;
- params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
- params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
- params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
+ params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
+ params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
+ params.is_write = ((vcpu->arch.hsr & 1) == 0);
params.is_64bit = true;
- params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 16) & 0xf;
+ params.Op1 = (vcpu->arch.hsr >> 16) & 0xf;
params.Op2 = 0;
- params.Rt2 = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
+ params.Rt2 = (vcpu->arch.hsr >> 10) & 0xf;
params.CRn = 0;
return emulate_cp15(vcpu, ¶ms);
@@ -347,14 +347,14 @@ int kvm_handle_cp15_32(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
struct coproc_params params;
- params.CRm = (kvm_vcpu_get_hsr(vcpu) >> 1) & 0xf;
- params.Rt1 = (kvm_vcpu_get_hsr(vcpu) >> 5) & 0xf;
- params.is_write = ((kvm_vcpu_get_hsr(vcpu) & 1) == 0);
+ params.CRm = (vcpu->arch.hsr >> 1) & 0xf;
+ params.Rt1 = (vcpu->arch.hsr >> 5) & 0xf;
+ params.is_write = ((vcpu->arch.hsr & 1) == 0);
params.is_64bit = false;
- params.CRn = (kvm_vcpu_get_hsr(vcpu) >> 10) & 0xf;
- params.Op1 = (kvm_vcpu_get_hsr(vcpu) >> 14) & 0x7;
- params.Op2 = (kvm_vcpu_get_hsr(vcpu) >> 17) & 0x7;
+ params.CRn = (vcpu->arch.hsr >> 10) & 0xf;
+ params.Op1 = (vcpu->arch.hsr >> 14) & 0x7;
+ params.Op2 = (vcpu->arch.hsr >> 17) & 0x7;
params.Rt2 = 0;
return emulate_cp15(vcpu, ¶ms);
diff --git a/trunk/arch/arm/kvm/coproc.h b/trunk/arch/arm/kvm/coproc.h
index b7301d3e4799..992adfafa2ff 100644
--- a/trunk/arch/arm/kvm/coproc.h
+++ b/trunk/arch/arm/kvm/coproc.h
@@ -84,7 +84,7 @@ static inline bool read_zero(struct kvm_vcpu *vcpu,
static inline bool write_to_read_only(struct kvm_vcpu *vcpu,
const struct coproc_params *params)
{
- kvm_debug("CP15 write to read-only register at: %08lx\n",
+ kvm_debug("CP15 write to read-only register at: %08x\n",
*vcpu_pc(vcpu));
print_cp_instr(params);
return false;
@@ -93,7 +93,7 @@ static inline bool write_to_read_only(struct kvm_vcpu *vcpu,
static inline bool read_from_write_only(struct kvm_vcpu *vcpu,
const struct coproc_params *params)
{
- kvm_debug("CP15 read to write-only register at: %08lx\n",
+ kvm_debug("CP15 read to write-only register at: %08x\n",
*vcpu_pc(vcpu));
print_cp_instr(params);
return false;
diff --git a/trunk/arch/arm/kvm/emulate.c b/trunk/arch/arm/kvm/emulate.c
index bdede9e7da51..d61450ac6665 100644
--- a/trunk/arch/arm/kvm/emulate.c
+++ b/trunk/arch/arm/kvm/emulate.c
@@ -20,7 +20,6 @@
#include
#include
#include
-#include
#include
#include "trace.h"
@@ -110,10 +109,10 @@ static const unsigned long vcpu_reg_offsets[VCPU_NR_MODES][15] = {
* Return a pointer to the register number valid in the current mode of
* the virtual CPU.
*/
-unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
+u32 *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
{
- unsigned long *reg_array = (unsigned long *)&vcpu->arch.regs;
- unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
+ u32 *reg_array = (u32 *)&vcpu->arch.regs;
+ u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
switch (mode) {
case USR_MODE...SVC_MODE:
@@ -142,9 +141,9 @@ unsigned long *vcpu_reg(struct kvm_vcpu *vcpu, u8 reg_num)
/*
* Return the SPSR for the current mode of the virtual CPU.
*/
-unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu)
+u32 *vcpu_spsr(struct kvm_vcpu *vcpu)
{
- unsigned long mode = *vcpu_cpsr(vcpu) & MODE_MASK;
+ u32 mode = *vcpu_cpsr(vcpu) & MODE_MASK;
switch (mode) {
case SVC_MODE:
return &vcpu->arch.regs.KVM_ARM_SVC_spsr;
@@ -161,48 +160,20 @@ unsigned long *vcpu_spsr(struct kvm_vcpu *vcpu)
}
}
-/*
- * A conditional instruction is allowed to trap, even though it
- * wouldn't be executed. So let's re-implement the hardware, in
- * software!
+/**
+ * kvm_handle_wfi - handle a wait-for-interrupts instruction executed by a guest
+ * @vcpu: the vcpu pointer
+ * @run: the kvm_run structure pointer
+ *
+ * Simply sets the wait_for_interrupts flag on the vcpu structure, which will
+ * halt execution of world-switches and schedule other host processes until
+ * there is an incoming IRQ or FIQ to the VM.
*/
-bool kvm_condition_valid(struct kvm_vcpu *vcpu)
+int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
- unsigned long cpsr, cond, insn;
-
- /*
- * Exception Code 0 can only happen if we set HCR.TGE to 1, to
- * catch undefined instructions, and then we won't get past
- * the arm_exit_handlers test anyway.
- */
- BUG_ON(!kvm_vcpu_trap_get_class(vcpu));
-
- /* Top two bits non-zero? Unconditional. */
- if (kvm_vcpu_get_hsr(vcpu) >> 30)
- return true;
-
- cpsr = *vcpu_cpsr(vcpu);
-
- /* Is condition field valid? */
- if ((kvm_vcpu_get_hsr(vcpu) & HSR_CV) >> HSR_CV_SHIFT)
- cond = (kvm_vcpu_get_hsr(vcpu) & HSR_COND) >> HSR_COND_SHIFT;
- else {
- /* This can happen in Thumb mode: examine IT state. */
- unsigned long it;
-
- it = ((cpsr >> 8) & 0xFC) | ((cpsr >> 25) & 0x3);
-
- /* it == 0 => unconditional. */
- if (it == 0)
- return true;
-
- /* The cond for this insn works out as the top 4 bits. */
- cond = (it >> 4);
- }
-
- /* Shift makes it look like an ARM-mode instruction */
- insn = cond << 28;
- return arm_check_condition(insn, cpsr) != ARM_OPCODE_CONDTEST_FAIL;
+ trace_kvm_wfi(*vcpu_pc(vcpu));
+ kvm_vcpu_block(vcpu);
+ return 1;
}
/**
@@ -286,9 +257,9 @@ static u32 exc_vector_base(struct kvm_vcpu *vcpu)
*/
void kvm_inject_undefined(struct kvm_vcpu *vcpu)
{
- unsigned long new_lr_value;
- unsigned long new_spsr_value;
- unsigned long cpsr = *vcpu_cpsr(vcpu);
+ u32 new_lr_value;
+ u32 new_spsr_value;
+ u32 cpsr = *vcpu_cpsr(vcpu);
u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
bool is_thumb = (cpsr & PSR_T_BIT);
u32 vect_offset = 4;
@@ -320,9 +291,9 @@ void kvm_inject_undefined(struct kvm_vcpu *vcpu)
*/
static void inject_abt(struct kvm_vcpu *vcpu, bool is_pabt, unsigned long addr)
{
- unsigned long new_lr_value;
- unsigned long new_spsr_value;
- unsigned long cpsr = *vcpu_cpsr(vcpu);
+ u32 new_lr_value;
+ u32 new_spsr_value;
+ u32 cpsr = *vcpu_cpsr(vcpu);
u32 sctlr = vcpu->arch.cp15[c1_SCTLR];
bool is_thumb = (cpsr & PSR_T_BIT);
u32 vect_offset;
diff --git a/trunk/arch/arm/kvm/guest.c b/trunk/arch/arm/kvm/guest.c
index 152d03612181..2339d9609d36 100644
--- a/trunk/arch/arm/kvm/guest.c
+++ b/trunk/arch/arm/kvm/guest.c
@@ -22,7 +22,6 @@
#include
#include
#include
-#include
#include
#include
#include
@@ -181,22 +180,6 @@ int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
return -EINVAL;
}
-int __attribute_const__ kvm_target_cpu(void)
-{
- unsigned long implementor = read_cpuid_implementor();
- unsigned long part_number = read_cpuid_part_number();
-
- if (implementor != ARM_CPU_IMP_ARM)
- return -EINVAL;
-
- switch (part_number) {
- case ARM_CPU_PART_CORTEX_A15:
- return KVM_ARM_TARGET_CORTEX_A15;
- default:
- return -EINVAL;
- }
-}
-
int kvm_vcpu_set_target(struct kvm_vcpu *vcpu,
const struct kvm_vcpu_init *init)
{
diff --git a/trunk/arch/arm/kvm/handle_exit.c b/trunk/arch/arm/kvm/handle_exit.c
deleted file mode 100644
index 3d74a0be47db..000000000000
--- a/trunk/arch/arm/kvm/handle_exit.c
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * Copyright (C) 2012 - Virtual Open Systems and Columbia University
- * Author: Christoffer Dall
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License, version 2, as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include
-#include
-#include
-#include
-#include
-#include
-#include
-
-#include "trace.h"
-
-#include "trace.h"
-
-typedef int (*exit_handle_fn)(struct kvm_vcpu *, struct kvm_run *);
-
-static int handle_svc_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- /* SVC called from Hyp mode should never get here */
- kvm_debug("SVC called from Hyp mode shouldn't go here\n");
- BUG();
- return -EINVAL; /* Squash warning */
-}
-
-static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- trace_kvm_hvc(*vcpu_pc(vcpu), *vcpu_reg(vcpu, 0),
- kvm_vcpu_hvc_get_imm(vcpu));
-
- if (kvm_psci_call(vcpu))
- return 1;
-
- kvm_inject_undefined(vcpu);
- return 1;
-}
-
-static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- if (kvm_psci_call(vcpu))
- return 1;
-
- kvm_inject_undefined(vcpu);
- return 1;
-}
-
-static int handle_pabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- /* The hypervisor should never cause aborts */
- kvm_err("Prefetch Abort taken from Hyp mode at %#08lx (HSR: %#08x)\n",
- kvm_vcpu_get_hfar(vcpu), kvm_vcpu_get_hsr(vcpu));
- return -EFAULT;
-}
-
-static int handle_dabt_hyp(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- /* This is either an error in the ws. code or an external abort */
- kvm_err("Data Abort taken from Hyp mode at %#08lx (HSR: %#08x)\n",
- kvm_vcpu_get_hfar(vcpu), kvm_vcpu_get_hsr(vcpu));
- return -EFAULT;
-}
-
-/**
- * kvm_handle_wfi - handle a wait-for-interrupts instruction executed by a guest
- * @vcpu: the vcpu pointer
- * @run: the kvm_run structure pointer
- *
- * Simply sets the wait_for_interrupts flag on the vcpu structure, which will
- * halt execution of world-switches and schedule other host processes until
- * there is an incoming IRQ or FIQ to the VM.
- */
-static int kvm_handle_wfi(struct kvm_vcpu *vcpu, struct kvm_run *run)
-{
- trace_kvm_wfi(*vcpu_pc(vcpu));
- kvm_vcpu_block(vcpu);
- return 1;
-}
-
-static exit_handle_fn arm_exit_handlers[] = {
- [HSR_EC_WFI] = kvm_handle_wfi,
- [HSR_EC_CP15_32] = kvm_handle_cp15_32,
- [HSR_EC_CP15_64] = kvm_handle_cp15_64,
- [HSR_EC_CP14_MR] = kvm_handle_cp14_access,
- [HSR_EC_CP14_LS] = kvm_handle_cp14_load_store,
- [HSR_EC_CP14_64] = kvm_handle_cp14_access,
- [HSR_EC_CP_0_13] = kvm_handle_cp_0_13_access,
- [HSR_EC_CP10_ID] = kvm_handle_cp10_id,
- [HSR_EC_SVC_HYP] = handle_svc_hyp,
- [HSR_EC_HVC] = handle_hvc,
- [HSR_EC_SMC] = handle_smc,
- [HSR_EC_IABT] = kvm_handle_guest_abort,
- [HSR_EC_IABT_HYP] = handle_pabt_hyp,
- [HSR_EC_DABT] = kvm_handle_guest_abort,
- [HSR_EC_DABT_HYP] = handle_dabt_hyp,
-};
-
-static exit_handle_fn kvm_get_exit_handler(struct kvm_vcpu *vcpu)
-{
- u8 hsr_ec = kvm_vcpu_trap_get_class(vcpu);
-
- if (hsr_ec >= ARRAY_SIZE(arm_exit_handlers) ||
- !arm_exit_handlers[hsr_ec]) {
- kvm_err("Unknown exception class: hsr: %#08x\n",
- (unsigned int)kvm_vcpu_get_hsr(vcpu));
- BUG();
- }
-
- return arm_exit_handlers[hsr_ec];
-}
-
-/*
- * Return > 0 to return to guest, < 0 on error, 0 (and set exit_reason) on
- * proper exit to userspace.
- */
-int handle_exit(struct kvm_vcpu *vcpu, struct kvm_run *run,
- int exception_index)
-{
- exit_handle_fn exit_handler;
-
- switch (exception_index) {
- case ARM_EXCEPTION_IRQ:
- return 1;
- case ARM_EXCEPTION_UNDEFINED:
- kvm_err("Undefined exception in Hyp mode at: %#08lx\n",
- kvm_vcpu_get_hyp_pc(vcpu));
- BUG();
- panic("KVM: Hypervisor undefined exception!\n");
- case ARM_EXCEPTION_DATA_ABORT:
- case ARM_EXCEPTION_PREF_ABORT:
- case ARM_EXCEPTION_HVC:
- /*
- * See ARM ARM B1.14.1: "Hyp traps on instructions
- * that fail their condition code check"
- */
- if (!kvm_condition_valid(vcpu)) {
- kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
- return 1;
- }
-
- exit_handler = kvm_get_exit_handler(vcpu);
-
- return exit_handler(vcpu, run);
- default:
- kvm_pr_unimpl("Unsupported exception type: %d",
- exception_index);
- run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
- return 0;
- }
-}
diff --git a/trunk/arch/arm/kvm/interrupts.S b/trunk/arch/arm/kvm/interrupts.S
index f7793df62f58..8ca87ab0919d 100644
--- a/trunk/arch/arm/kvm/interrupts.S
+++ b/trunk/arch/arm/kvm/interrupts.S
@@ -35,18 +35,15 @@ __kvm_hyp_code_start:
/********************************************************************
* Flush per-VMID TLBs
*
- * void __kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa);
+ * void __kvm_tlb_flush_vmid(struct kvm *kvm);
*
* We rely on the hardware to broadcast the TLB invalidation to all CPUs
* inside the inner-shareable domain (which is the case for all v7
* implementations). If we come across a non-IS SMP implementation, we'll
* have to use an IPI based mechanism. Until then, we stick to the simple
* hardware assisted version.
- *
- * As v7 does not support flushing per IPA, just nuke the whole TLB
- * instead, ignoring the ipa value.
*/
-ENTRY(__kvm_tlb_flush_vmid_ipa)
+ENTRY(__kvm_tlb_flush_vmid)
push {r2, r3}
add r0, r0, #KVM_VTTBR
@@ -63,7 +60,7 @@ ENTRY(__kvm_tlb_flush_vmid_ipa)
pop {r2, r3}
bx lr
-ENDPROC(__kvm_tlb_flush_vmid_ipa)
+ENDPROC(__kvm_tlb_flush_vmid)
/********************************************************************
* Flush TLBs and instruction caches of all CPUs inside the inner-shareable
@@ -238,9 +235,9 @@ ENTRY(kvm_call_hyp)
* instruction is issued since all traps are disabled when running the host
* kernel as per the Hyp-mode initialization at boot time.
*
- * HVC instructions cause a trap to the vector page + offset 0x14 (see hyp_hvc
+ * HVC instructions cause a trap to the vector page + offset 0x18 (see hyp_hvc
* below) when the HVC instruction is called from SVC mode (i.e. a guest or the
- * host kernel) and they cause a trap to the vector page + offset 0x8 when HVC
+ * host kernel) and they cause a trap to the vector page + offset 0xc when HVC
* instructions are called from within Hyp-mode.
*
* Hyp-ABI: Calling HYP-mode functions from host (in SVC mode):
diff --git a/trunk/arch/arm/kvm/mmio.c b/trunk/arch/arm/kvm/mmio.c
index 72a12f2171b2..98a870ff1a5c 100644
--- a/trunk/arch/arm/kvm/mmio.c
+++ b/trunk/arch/arm/kvm/mmio.c
@@ -33,16 +33,16 @@
*/
int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
- unsigned long *dest;
+ __u32 *dest;
unsigned int len;
int mask;
if (!run->mmio.is_write) {
dest = vcpu_reg(vcpu, vcpu->arch.mmio_decode.rt);
- *dest = 0;
+ memset(dest, 0, sizeof(int));
len = run->mmio.len;
- if (len > sizeof(unsigned long))
+ if (len > 4)
return -EINVAL;
memcpy(dest, run->mmio.data, len);
@@ -50,8 +50,7 @@ int kvm_handle_mmio_return(struct kvm_vcpu *vcpu, struct kvm_run *run)
trace_kvm_mmio(KVM_TRACE_MMIO_READ, len, run->mmio.phys_addr,
*((u64 *)run->mmio.data));
- if (vcpu->arch.mmio_decode.sign_extend &&
- len < sizeof(unsigned long)) {
+ if (vcpu->arch.mmio_decode.sign_extend && len < 4) {
mask = 1U << ((len * 8) - 1);
*dest = (*dest ^ mask) - mask;
}
@@ -66,29 +65,40 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
unsigned long rt, len;
bool is_write, sign_extend;
- if (kvm_vcpu_dabt_isextabt(vcpu)) {
+ if ((vcpu->arch.hsr >> 8) & 1) {
/* cache operation on I/O addr, tell guest unsupported */
- kvm_inject_dabt(vcpu, kvm_vcpu_get_hfar(vcpu));
+ kvm_inject_dabt(vcpu, vcpu->arch.hxfar);
return 1;
}
- if (kvm_vcpu_dabt_iss1tw(vcpu)) {
+ if ((vcpu->arch.hsr >> 7) & 1) {
/* page table accesses IO mem: tell guest to fix its TTBR */
- kvm_inject_dabt(vcpu, kvm_vcpu_get_hfar(vcpu));
+ kvm_inject_dabt(vcpu, vcpu->arch.hxfar);
return 1;
}
- len = kvm_vcpu_dabt_get_as(vcpu);
- if (unlikely(len < 0))
- return len;
+ switch ((vcpu->arch.hsr >> 22) & 0x3) {
+ case 0:
+ len = 1;
+ break;
+ case 1:
+ len = 2;
+ break;
+ case 2:
+ len = 4;
+ break;
+ default:
+ kvm_err("Hardware is weird: SAS 0b11 is reserved\n");
+ return -EFAULT;
+ }
- is_write = kvm_vcpu_dabt_iswrite(vcpu);
- sign_extend = kvm_vcpu_dabt_issext(vcpu);
- rt = kvm_vcpu_dabt_get_rd(vcpu);
+ is_write = vcpu->arch.hsr & HSR_WNR;
+ sign_extend = vcpu->arch.hsr & HSR_SSE;
+ rt = (vcpu->arch.hsr & HSR_SRT_MASK) >> HSR_SRT_SHIFT;
if (kvm_vcpu_reg_is_pc(vcpu, rt)) {
/* IO memory trying to read/write pc */
- kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
+ kvm_inject_pabt(vcpu, vcpu->arch.hxfar);
return 1;
}
@@ -102,7 +112,7 @@ static int decode_hsr(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
* The MMIO instruction is emulated and should not be re-executed
* in the guest.
*/
- kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
+ kvm_skip_instr(vcpu, (vcpu->arch.hsr >> 25) & 1);
return 0;
}
@@ -120,7 +130,7 @@ int io_mem_abort(struct kvm_vcpu *vcpu, struct kvm_run *run,
* space do its magic.
*/
- if (kvm_vcpu_dabt_isvalid(vcpu)) {
+ if (vcpu->arch.hsr & HSR_ISV) {
ret = decode_hsr(vcpu, fault_ipa, &mmio);
if (ret)
return ret;
diff --git a/trunk/arch/arm/kvm/mmu.c b/trunk/arch/arm/kvm/mmu.c
index 2f12e4056408..99e07c7dd745 100644
--- a/trunk/arch/arm/kvm/mmu.c
+++ b/trunk/arch/arm/kvm/mmu.c
@@ -20,6 +20,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -27,6 +28,8 @@
#include
#include
#include
+#include
+#include
#include "trace.h"
@@ -34,9 +37,19 @@ extern char __hyp_idmap_text_start[], __hyp_idmap_text_end[];
static DEFINE_MUTEX(kvm_hyp_pgd_mutex);
-static void kvm_tlb_flush_vmid_ipa(struct kvm *kvm, phys_addr_t ipa)
+static void kvm_tlb_flush_vmid(struct kvm *kvm)
{
- kvm_call_hyp(__kvm_tlb_flush_vmid_ipa, kvm, ipa);
+ kvm_call_hyp(__kvm_tlb_flush_vmid, kvm);
+}
+
+static void kvm_set_pte(pte_t *pte, pte_t new_pte)
+{
+ pte_val(*pte) = new_pte;
+ /*
+ * flush_pmd_entry just takes a void pointer and cleans the necessary
+ * cache entries, so we can reuse the function for ptes.
+ */
+ flush_pmd_entry(pte);
}
static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
@@ -85,42 +98,33 @@ static void free_ptes(pmd_t *pmd, unsigned long addr)
}
}
-static void free_hyp_pgd_entry(unsigned long addr)
-{
- pgd_t *pgd;
- pud_t *pud;
- pmd_t *pmd;
- unsigned long hyp_addr = KERN_TO_HYP(addr);
-
- pgd = hyp_pgd + pgd_index(hyp_addr);
- pud = pud_offset(pgd, hyp_addr);
-
- if (pud_none(*pud))
- return;
- BUG_ON(pud_bad(*pud));
-
- pmd = pmd_offset(pud, hyp_addr);
- free_ptes(pmd, addr);
- pmd_free(NULL, pmd);
- pud_clear(pud);
-}
-
/**
* free_hyp_pmds - free a Hyp-mode level-2 tables and child level-3 tables
*
* Assumes this is a page table used strictly in Hyp-mode and therefore contains
- * either mappings in the kernel memory area (above PAGE_OFFSET), or
- * device mappings in the vmalloc range (from VMALLOC_START to VMALLOC_END).
+ * only mappings in the kernel memory area, which is above PAGE_OFFSET.
*/
void free_hyp_pmds(void)
{
+ pgd_t *pgd;
+ pud_t *pud;
+ pmd_t *pmd;
unsigned long addr;
mutex_lock(&kvm_hyp_pgd_mutex);
- for (addr = PAGE_OFFSET; virt_addr_valid(addr); addr += PGDIR_SIZE)
- free_hyp_pgd_entry(addr);
- for (addr = VMALLOC_START; is_vmalloc_addr((void*)addr); addr += PGDIR_SIZE)
- free_hyp_pgd_entry(addr);
+ for (addr = PAGE_OFFSET; addr != 0; addr += PGDIR_SIZE) {
+ pgd = hyp_pgd + pgd_index(addr);
+ pud = pud_offset(pgd, addr);
+
+ if (pud_none(*pud))
+ continue;
+ BUG_ON(pud_bad(*pud));
+
+ pmd = pmd_offset(pud, addr);
+ free_ptes(pmd, addr);
+ pmd_free(NULL, pmd);
+ pud_clear(pud);
+ }
mutex_unlock(&kvm_hyp_pgd_mutex);
}
@@ -132,9 +136,7 @@ static void create_hyp_pte_mappings(pmd_t *pmd, unsigned long start,
struct page *page;
for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
- unsigned long hyp_addr = KERN_TO_HYP(addr);
-
- pte = pte_offset_kernel(pmd, hyp_addr);
+ pte = pte_offset_kernel(pmd, addr);
BUG_ON(!virt_addr_valid(addr));
page = virt_to_page(addr);
kvm_set_pte(pte, mk_pte(page, PAGE_HYP));
@@ -149,9 +151,7 @@ static void create_hyp_io_pte_mappings(pmd_t *pmd, unsigned long start,
unsigned long addr;
for (addr = start & PAGE_MASK; addr < end; addr += PAGE_SIZE) {
- unsigned long hyp_addr = KERN_TO_HYP(addr);
-
- pte = pte_offset_kernel(pmd, hyp_addr);
+ pte = pte_offset_kernel(pmd, addr);
BUG_ON(pfn_valid(*pfn_base));
kvm_set_pte(pte, pfn_pte(*pfn_base, PAGE_HYP_DEVICE));
(*pfn_base)++;
@@ -166,13 +166,12 @@ static int create_hyp_pmd_mappings(pud_t *pud, unsigned long start,
unsigned long addr, next;
for (addr = start; addr < end; addr = next) {
- unsigned long hyp_addr = KERN_TO_HYP(addr);
- pmd = pmd_offset(pud, hyp_addr);
+ pmd = pmd_offset(pud, addr);
BUG_ON(pmd_sect(*pmd));
if (pmd_none(*pmd)) {
- pte = pte_alloc_one_kernel(NULL, hyp_addr);
+ pte = pte_alloc_one_kernel(NULL, addr);
if (!pte) {
kvm_err("Cannot allocate Hyp pte\n");
return -ENOMEM;
@@ -207,23 +206,17 @@ static int __create_hyp_mappings(void *from, void *to, unsigned long *pfn_base)
unsigned long addr, next;
int err = 0;
- if (start >= end)
- return -EINVAL;
- /* Check for a valid kernel memory mapping */
- if (!pfn_base && (!virt_addr_valid(from) || !virt_addr_valid(to - 1)))
- return -EINVAL;
- /* Check for a valid kernel IO mapping */
- if (pfn_base && (!is_vmalloc_addr(from) || !is_vmalloc_addr(to - 1)))
+ BUG_ON(start > end);
+ if (start < PAGE_OFFSET)
return -EINVAL;
mutex_lock(&kvm_hyp_pgd_mutex);
for (addr = start; addr < end; addr = next) {
- unsigned long hyp_addr = KERN_TO_HYP(addr);
- pgd = hyp_pgd + pgd_index(hyp_addr);
- pud = pud_offset(pgd, hyp_addr);
+ pgd = hyp_pgd + pgd_index(addr);
+ pud = pud_offset(pgd, addr);
if (pud_none_or_clear_bad(pud)) {
- pmd = pmd_alloc_one(NULL, hyp_addr);
+ pmd = pmd_alloc_one(NULL, addr);
if (!pmd) {
kvm_err("Cannot allocate Hyp pmd\n");
err = -ENOMEM;
@@ -243,13 +236,12 @@ static int __create_hyp_mappings(void *from, void *to, unsigned long *pfn_base)
}
/**
- * create_hyp_mappings - duplicate a kernel virtual address range in Hyp mode
+ * create_hyp_mappings - map a kernel virtual address range in Hyp mode
* @from: The virtual kernel start address of the range
* @to: The virtual kernel end address of the range (exclusive)
*
- * The same virtual address as the kernel virtual address is also used
- * in Hyp-mode mapping (modulo HYP_PAGE_OFFSET) to the same underlying
- * physical pages.
+ * The same virtual address as the kernel virtual address is also used in
+ * Hyp-mode mapping to the same underlying physical pages.
*
* Note: Wrapping around zero in the "to" address is not supported.
*/
@@ -259,13 +251,10 @@ int create_hyp_mappings(void *from, void *to)
}
/**
- * create_hyp_io_mappings - duplicate a kernel IO mapping into Hyp mode
- * @from: The kernel start VA of the range
- * @to: The kernel end VA of the range (exclusive)
+ * create_hyp_io_mappings - map a physical IO range in Hyp mode
+ * @from: The virtual HYP start address of the range
+ * @to: The virtual HYP end address of the range (exclusive)
* @addr: The physical start address which gets mapped
- *
- * The resulting HYP VA is the same as the kernel VA, modulo
- * HYP_PAGE_OFFSET.
*/
int create_hyp_io_mappings(void *from, void *to, phys_addr_t addr)
{
@@ -301,7 +290,7 @@ int kvm_alloc_stage2_pgd(struct kvm *kvm)
VM_BUG_ON((unsigned long)pgd & (S2_PGD_SIZE - 1));
memset(pgd, 0, PTRS_PER_S2_PGD * sizeof(pgd_t));
- kvm_clean_pgd(pgd);
+ clean_dcache_area(pgd, PTRS_PER_S2_PGD * sizeof(pgd_t));
kvm->arch.pgd = pgd;
return 0;
@@ -433,22 +422,22 @@ static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
return 0; /* ignore calls from kvm_set_spte_hva */
pmd = mmu_memory_cache_alloc(cache);
pud_populate(NULL, pud, pmd);
+ pmd += pmd_index(addr);
get_page(virt_to_page(pud));
- }
-
- pmd = pmd_offset(pud, addr);
+ } else
+ pmd = pmd_offset(pud, addr);
/* Create 2nd stage page table mapping - Level 2 */
if (pmd_none(*pmd)) {
if (!cache)
return 0; /* ignore calls from kvm_set_spte_hva */
pte = mmu_memory_cache_alloc(cache);
- kvm_clean_pte(pte);
+ clean_pte_table(pte);
pmd_populate_kernel(NULL, pmd, pte);
+ pte += pte_index(addr);
get_page(virt_to_page(pmd));
- }
-
- pte = pte_offset_kernel(pmd, addr);
+ } else
+ pte = pte_offset_kernel(pmd, addr);
if (iomap && pte_present(*pte))
return -EFAULT;
@@ -457,7 +446,7 @@ static int stage2_set_pte(struct kvm *kvm, struct kvm_mmu_memory_cache *cache,
old_pte = *pte;
kvm_set_pte(pte, *new_pte);
if (pte_present(old_pte))
- kvm_tlb_flush_vmid_ipa(kvm, addr);
+ kvm_tlb_flush_vmid(kvm);
else
get_page(virt_to_page(pte));
@@ -484,8 +473,7 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
pfn = __phys_to_pfn(pa);
for (addr = guest_ipa; addr < end; addr += PAGE_SIZE) {
- pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE);
- kvm_set_s2pte_writable(&pte);
+ pte_t pte = pfn_pte(pfn, PAGE_S2_DEVICE | L_PTE_S2_RDWR);
ret = mmu_topup_memory_cache(&cache, 2, 2);
if (ret)
@@ -504,6 +492,29 @@ int kvm_phys_addr_ioremap(struct kvm *kvm, phys_addr_t guest_ipa,
return ret;
}
+static void coherent_icache_guest_page(struct kvm *kvm, gfn_t gfn)
+{
+ /*
+ * If we are going to insert an instruction page and the icache is
+ * either VIPT or PIPT, there is a potential problem where the host
+ * (or another VM) may have used the same page as this guest, and we
+ * read incorrect data from the icache. If we're using a PIPT cache,
+ * we can invalidate just that page, but if we are using a VIPT cache
+ * we need to invalidate the entire icache - damn shame - as written
+ * in the ARM ARM (DDI 0406C.b - Page B3-1393).
+ *
+ * VIVT caches are tagged using both the ASID and the VMID and doesn't
+ * need any kind of flushing (DDI 0406C.b - Page B3-1392).
+ */
+ if (icache_is_pipt()) {
+ unsigned long hva = gfn_to_hva(kvm, gfn);
+ __cpuc_coherent_user_range(hva, hva + PAGE_SIZE);
+ } else if (!icache_is_vivt_asid_tagged()) {
+ /* any kind of VIPT cache */
+ __flush_icache_all();
+ }
+}
+
static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
gfn_t gfn, struct kvm_memory_slot *memslot,
unsigned long fault_status)
@@ -515,7 +526,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
unsigned long mmu_seq;
struct kvm_mmu_memory_cache *memcache = &vcpu->arch.mmu_page_cache;
- write_fault = kvm_is_write_fault(kvm_vcpu_get_hsr(vcpu));
+ write_fault = kvm_is_write_fault(vcpu->arch.hsr);
if (fault_status == FSC_PERM && !write_fault) {
kvm_err("Unexpected L2 read permission error\n");
return -EFAULT;
@@ -549,7 +560,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
if (mmu_notifier_retry(vcpu->kvm, mmu_seq))
goto out_unlock;
if (writable) {
- kvm_set_s2pte_writable(&new_pte);
+ pte_val(new_pte) |= L_PTE_S2_RDWR;
kvm_set_pfn_dirty(pfn);
}
stage2_set_pte(vcpu->kvm, memcache, fault_ipa, &new_pte, false);
@@ -574,6 +585,7 @@ static int user_mem_abort(struct kvm_vcpu *vcpu, phys_addr_t fault_ipa,
*/
int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
+ unsigned long hsr_ec;
unsigned long fault_status;
phys_addr_t fault_ipa;
struct kvm_memory_slot *memslot;
@@ -581,17 +593,18 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
gfn_t gfn;
int ret, idx;
- is_iabt = kvm_vcpu_trap_is_iabt(vcpu);
- fault_ipa = kvm_vcpu_get_fault_ipa(vcpu);
+ hsr_ec = vcpu->arch.hsr >> HSR_EC_SHIFT;
+ is_iabt = (hsr_ec == HSR_EC_IABT);
+ fault_ipa = ((phys_addr_t)vcpu->arch.hpfar & HPFAR_MASK) << 8;
- trace_kvm_guest_fault(*vcpu_pc(vcpu), kvm_vcpu_get_hsr(vcpu),
- kvm_vcpu_get_hfar(vcpu), fault_ipa);
+ trace_kvm_guest_fault(*vcpu_pc(vcpu), vcpu->arch.hsr,
+ vcpu->arch.hxfar, fault_ipa);
/* Check the stage-2 fault is trans. fault or write fault */
- fault_status = kvm_vcpu_trap_get_fault(vcpu);
+ fault_status = (vcpu->arch.hsr & HSR_FSC_TYPE);
if (fault_status != FSC_FAULT && fault_status != FSC_PERM) {
- kvm_err("Unsupported fault status: EC=%#x DFCS=%#lx\n",
- kvm_vcpu_trap_get_class(vcpu), fault_status);
+ kvm_err("Unsupported fault status: EC=%#lx DFCS=%#lx\n",
+ hsr_ec, fault_status);
return -EFAULT;
}
@@ -601,7 +614,7 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
if (!kvm_is_visible_gfn(vcpu->kvm, gfn)) {
if (is_iabt) {
/* Prefetch Abort on I/O address */
- kvm_inject_pabt(vcpu, kvm_vcpu_get_hfar(vcpu));
+ kvm_inject_pabt(vcpu, vcpu->arch.hxfar);
ret = 1;
goto out_unlock;
}
@@ -613,13 +626,8 @@ int kvm_handle_guest_abort(struct kvm_vcpu *vcpu, struct kvm_run *run)
goto out_unlock;
}
- /*
- * The IPA is reported as [MAX:12], so we need to
- * complement it with the bottom 12 bits from the
- * faulting VA. This is always 12 bits, irrespective
- * of the page size.
- */
- fault_ipa |= kvm_vcpu_get_hfar(vcpu) & ((1 << 12) - 1);
+ /* Adjust page offset */
+ fault_ipa |= vcpu->arch.hxfar & ~PAGE_MASK;
ret = io_mem_abort(vcpu, run, fault_ipa);
goto out_unlock;
}
@@ -674,7 +682,7 @@ static void handle_hva_to_gpa(struct kvm *kvm,
static void kvm_unmap_hva_handler(struct kvm *kvm, gpa_t gpa, void *data)
{
unmap_stage2_range(kvm, gpa, PAGE_SIZE);
- kvm_tlb_flush_vmid_ipa(kvm, gpa);
+ kvm_tlb_flush_vmid(kvm);
}
int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
@@ -768,7 +776,7 @@ void kvm_clear_hyp_idmap(void)
pmd = pmd_offset(pud, addr);
pud_clear(pud);
- kvm_clean_pmd_entry(pmd);
+ clean_pmd_entry(pmd);
pmd_free(NULL, (pmd_t *)((unsigned long)pmd & PAGE_MASK));
} while (pgd++, addr = next, addr < end);
}
diff --git a/trunk/arch/arm/kvm/vgic.c b/trunk/arch/arm/kvm/vgic.c
index 17c5ac7d10ed..0e4cfe123b38 100644
--- a/trunk/arch/arm/kvm/vgic.c
+++ b/trunk/arch/arm/kvm/vgic.c
@@ -1477,7 +1477,7 @@ int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
if (addr & ~KVM_PHYS_MASK)
return -E2BIG;
- if (addr & (SZ_4K - 1))
+ if (addr & ~PAGE_MASK)
return -EINVAL;
mutex_lock(&kvm->lock);
diff --git a/trunk/arch/arm/mach-at91/at91sam9261.c b/trunk/arch/arm/mach-at91/at91sam9261.c
index 25efb5ac30f1..ac7a341bd0ff 100644
--- a/trunk/arch/arm/mach-at91/at91sam9261.c
+++ b/trunk/arch/arm/mach-at91/at91sam9261.c
@@ -169,8 +169,6 @@ static struct clk *periph_clocks[] __initdata = {
};
static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("hclk", "at91sam9261-lcdfb.0", &hck1),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g10-lcdfb.0", &hck1),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.1", &spi1_clk),
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
diff --git a/trunk/arch/arm/mach-at91/at91sam9261_devices.c b/trunk/arch/arm/mach-at91/at91sam9261_devices.c
index 629ea5fc95cf..92e0f861084a 100644
--- a/trunk/arch/arm/mach-at91/at91sam9261_devices.c
+++ b/trunk/arch/arm/mach-at91/at91sam9261_devices.c
@@ -488,6 +488,7 @@ static struct resource lcdc_resources[] = {
};
static struct platform_device at91_lcdc_device = {
+ .name = "atmel_lcdfb",
.id = 0,
.dev = {
.dma_mask = &lcdc_dmamask,
@@ -504,11 +505,6 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
return;
}
- if (cpu_is_at91sam9g10())
- at91_lcdc_device.name = "at91sam9g10-lcdfb";
- else
- at91_lcdc_device.name = "at91sam9261-lcdfb";
-
#if defined(CONFIG_FB_ATMEL_STN)
at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */
at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */
diff --git a/trunk/arch/arm/mach-at91/at91sam9263.c b/trunk/arch/arm/mach-at91/at91sam9263.c
index f44ffd2105a7..8e2d9f4a9a45 100644
--- a/trunk/arch/arm/mach-at91/at91sam9263.c
+++ b/trunk/arch/arm/mach-at91/at91sam9263.c
@@ -190,7 +190,6 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_DEV_ID("pclk", "at91rm9200_ssc.1", &ssc1_clk),
CLKDEV_CON_DEV_ID("pclk", "fff98000.ssc", &ssc0_clk),
CLKDEV_CON_DEV_ID("pclk", "fff9c000.ssc", &ssc1_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9263-lcdfb.0", &lcdc_clk),
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.0", &mmc0_clk),
CLKDEV_CON_DEV_ID("mci_clk", "atmel_mci.1", &mmc1_clk),
CLKDEV_CON_DEV_ID("spi_clk", "atmel_spi.0", &spi0_clk),
diff --git a/trunk/arch/arm/mach-at91/at91sam9263_devices.c b/trunk/arch/arm/mach-at91/at91sam9263_devices.c
index 858c8aac2daf..ed666f5cb01d 100644
--- a/trunk/arch/arm/mach-at91/at91sam9263_devices.c
+++ b/trunk/arch/arm/mach-at91/at91sam9263_devices.c
@@ -848,7 +848,7 @@ static struct resource lcdc_resources[] = {
};
static struct platform_device at91_lcdc_device = {
- .name = "at91sam9263-lcdfb",
+ .name = "atmel_lcdfb",
.id = 0,
.dev = {
.dma_mask = &lcdc_dmamask,
diff --git a/trunk/arch/arm/mach-at91/at91sam9g45.c b/trunk/arch/arm/mach-at91/at91sam9g45.c
index 8b7fce067652..a6c224fc9542 100644
--- a/trunk/arch/arm/mach-at91/at91sam9g45.c
+++ b/trunk/arch/arm/mach-at91/at91sam9g45.c
@@ -228,8 +228,6 @@ static struct clk_lookup periph_clocks_lookups[] = {
CLKDEV_CON_ID("hclk", &macb_clk),
/* One additional fake clock for ohci */
CLKDEV_CON_ID("ohci_clk", &uhphs_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g45-lcdfb.0", &lcdc_clk),
- CLKDEV_CON_DEV_ID("hclk", "at91sam9g45es-lcdfb.0", &lcdc_clk),
CLKDEV_CON_DEV_ID("ehci_clk", "atmel-ehci", &uhphs_clk),
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
diff --git a/trunk/arch/arm/mach-at91/at91sam9g45_devices.c b/trunk/arch/arm/mach-at91/at91sam9g45_devices.c
index acb703e13331..f0bf68268ca2 100644
--- a/trunk/arch/arm/mach-at91/at91sam9g45_devices.c
+++ b/trunk/arch/arm/mach-at91/at91sam9g45_devices.c
@@ -981,6 +981,7 @@ static struct resource lcdc_resources[] = {
};
static struct platform_device at91_lcdc_device = {
+ .name = "atmel_lcdfb",
.id = 0,
.dev = {
.dma_mask = &lcdc_dmamask,
@@ -996,11 +997,6 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
if (!data)
return;
- if (cpu_is_at91sam9g45es())
- at91_lcdc_device.name = "at91sam9g45es-lcdfb";
- else
- at91_lcdc_device.name = "at91sam9g45-lcdfb";
-
at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
diff --git a/trunk/arch/arm/mach-at91/at91sam9rl.c b/trunk/arch/arm/mach-at91/at91sam9rl.c
index f77fae5591bc..c39600764236 100644
--- a/trunk/arch/arm/mach-at91/at91sam9rl.c
+++ b/trunk/arch/arm/mach-at91/at91sam9rl.c
@@ -179,7 +179,6 @@ static struct clk *periph_clocks[] __initdata = {
};
static struct clk_lookup periph_clocks_lookups[] = {
- CLKDEV_CON_DEV_ID("hclk", "at91sam9rl-lcdfb.0", &lcdc_clk),
CLKDEV_CON_DEV_ID("hclk", "atmel_usba_udc", &utmi_clk),
CLKDEV_CON_DEV_ID("pclk", "atmel_usba_udc", &udphs_clk),
CLKDEV_CON_DEV_ID("t0_clk", "atmel_tcb.0", &tc0_clk),
diff --git a/trunk/arch/arm/mach-at91/at91sam9rl_devices.c b/trunk/arch/arm/mach-at91/at91sam9rl_devices.c
index 352468f265a9..ddf223ff35c4 100644
--- a/trunk/arch/arm/mach-at91/at91sam9rl_devices.c
+++ b/trunk/arch/arm/mach-at91/at91sam9rl_devices.c
@@ -514,7 +514,7 @@ static struct resource lcdc_resources[] = {
};
static struct platform_device at91_lcdc_device = {
- .name = "at91sam9rl-lcdfb",
+ .name = "atmel_lcdfb",
.id = 0,
.dev = {
.dma_mask = &lcdc_dmamask,
diff --git a/trunk/arch/arm/mach-bcm/Makefile b/trunk/arch/arm/mach-bcm/Makefile
index 6adb6aecf48f..bbf412261e5e 100644
--- a/trunk/arch/arm/mach-bcm/Makefile
+++ b/trunk/arch/arm/mach-bcm/Makefile
@@ -10,6 +10,4 @@
# of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
-obj-$(CONFIG_ARCH_BCM) := board_bcm.o bcm_kona_smc.o bcm_kona_smc_asm.o
-plus_sec := $(call as-instr,.arch_extension sec,+sec)
-AFLAGS_bcm_kona_smc_asm.o :=-Wa,-march=armv7-a$(plus_sec)
+obj-$(CONFIG_ARCH_BCM) := board_bcm.o
diff --git a/trunk/arch/arm/mach-bcm/bcm_kona_smc.c b/trunk/arch/arm/mach-bcm/bcm_kona_smc.c
deleted file mode 100644
index 56d9d19b2470..000000000000
--- a/trunk/arch/arm/mach-bcm/bcm_kona_smc.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include
-#include
-#include
-#include
-
-#include
-#include
-
-#include "bcm_kona_smc.h"
-
-struct secure_bridge_data {
- void __iomem *bounce; /* virtual address */
- u32 __iomem buffer_addr; /* physical address */
- int initialized;
-} bridge_data;
-
-struct bcm_kona_smc_data {
- unsigned service_id;
- unsigned arg0;
- unsigned arg1;
- unsigned arg2;
- unsigned arg3;
-};
-
-static const struct of_device_id bcm_kona_smc_ids[] __initconst = {
- {.compatible = "bcm,kona-smc"},
- {},
-};
-
-/* Map in the bounce area */
-void __init bcm_kona_smc_init(void)
-{
- struct device_node *node;
-
- /* Read buffer addr and size from the device tree node */
- node = of_find_matching_node(NULL, bcm_kona_smc_ids);
- BUG_ON(!node);
-
- /* Don't care about size or flags of the DT node */
- bridge_data.buffer_addr =
- be32_to_cpu(*of_get_address(node, 0, NULL, NULL));
- BUG_ON(!bridge_data.buffer_addr);
-
- bridge_data.bounce = of_iomap(node, 0);
- BUG_ON(!bridge_data.bounce);
-
- bridge_data.initialized = 1;
-
- pr_info("Secure API initialized!\n");
-}
-
-/* __bcm_kona_smc() should only run on CPU 0, with pre-emption disabled */
-static void __bcm_kona_smc(void *info)
-{
- struct bcm_kona_smc_data *data = info;
- u32 *args = bridge_data.bounce;
- int rc = 0;
-
- /* Must run on CPU 0 */
- BUG_ON(smp_processor_id() != 0);
-
- /* Check map in the bounce area */
- BUG_ON(!bridge_data.initialized);
-
- /* Copy one 32 bit word into the bounce area */
- args[0] = data->arg0;
- args[1] = data->arg1;
- args[2] = data->arg2;
- args[3] = data->arg3;
-
- /* Flush caches for input data passed to Secure Monitor */
- if (data->service_id != SSAPI_BRCM_START_VC_CORE)
- flush_cache_all();
-
- /* Trap into Secure Monitor */
- rc = bcm_kona_smc_asm(data->service_id, bridge_data.buffer_addr);
-
- if (rc != SEC_ROM_RET_OK)
- pr_err("Secure Monitor call failed (0x%x)!\n", rc);
-}
-
-unsigned bcm_kona_smc(unsigned service_id, unsigned arg0, unsigned arg1,
- unsigned arg2, unsigned arg3)
-{
- struct bcm_kona_smc_data data;
-
- data.service_id = service_id;
- data.arg0 = arg0;
- data.arg1 = arg1;
- data.arg2 = arg2;
- data.arg3 = arg3;
-
- /*
- * Due to a limitation of the secure monitor, we must use the SMP
- * infrastructure to forward all secure monitor calls to Core 0.
- */
- if (get_cpu() != 0)
- smp_call_function_single(0, __bcm_kona_smc, (void *)&data, 1);
- else
- __bcm_kona_smc(&data);
-
- put_cpu();
-
- return 0;
-}
diff --git a/trunk/arch/arm/mach-bcm/bcm_kona_smc.h b/trunk/arch/arm/mach-bcm/bcm_kona_smc.h
deleted file mode 100644
index 3bedbed1c21b..000000000000
--- a/trunk/arch/arm/mach-bcm/bcm_kona_smc.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef BCM_KONA_SMC_H
-#define BCM_KONA_SMC_H
-
-#include
-#define FLAGS (SEC_ROM_ICACHE_ENABLE_MASK | SEC_ROM_DCACHE_ENABLE_MASK | \
- SEC_ROM_IRQ_ENABLE_MASK | SEC_ROM_FIQ_ENABLE_MASK)
-
-/*!
- * Definitions for IRQ & FIQ Mask for ARM
- */
-
-#define FIQ_IRQ_MASK 0xC0
-#define FIQ_MASK 0x40
-#define IRQ_MASK 0x80
-
-/*!
- * Secure Mode FLAGs
- */
-
-/* When set, enables ICache within the secure mode */
-#define SEC_ROM_ICACHE_ENABLE_MASK 0x00000001
-
-/* When set, enables DCache within the secure mode */
-#define SEC_ROM_DCACHE_ENABLE_MASK 0x00000002
-
-/* When set, enables IRQ within the secure mode */
-#define SEC_ROM_IRQ_ENABLE_MASK 0x00000004
-
-/* When set, enables FIQ within the secure mode */
-#define SEC_ROM_FIQ_ENABLE_MASK 0x00000008
-
-/* When set, enables Unified L2 cache within the secure mode */
-#define SEC_ROM_UL2_CACHE_ENABLE_MASK 0x00000010
-
-/* Broadcom Secure Service API Service IDs */
-#define SSAPI_DORMANT_ENTRY_SERV 0x01000000
-#define SSAPI_PUBLIC_OTP_SERV 0x01000001
-#define SSAPI_ENABLE_L2_CACHE 0x01000002
-#define SSAPI_DISABLE_L2_CACHE 0x01000003
-#define SSAPI_WRITE_SCU_STATUS 0x01000004
-#define SSAPI_WRITE_PWR_GATE 0x01000005
-
-/* Broadcom Secure Service API Return Codes */
-#define SEC_ROM_RET_OK 0x00000001
-#define SEC_ROM_RET_FAIL 0x00000009
-
-#define SSAPI_RET_FROM_INT_SERV 0x4
-#define SEC_EXIT_NORMAL 0x1
-
-#define SSAPI_ROW_AES 0x0E000006
-#define SSAPI_BRCM_START_VC_CORE 0x0E000008
-
-#ifndef __ASSEMBLY__
-extern void bcm_kona_smc_init(void);
-
-extern unsigned bcm_kona_smc(unsigned service_id,
- unsigned arg0,
- unsigned arg1,
- unsigned arg2,
- unsigned arg3);
-
-extern int bcm_kona_smc_asm(u32 service_id,
- u32 buffer_addr);
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* BCM_KONA_SMC_H */
diff --git a/trunk/arch/arm/mach-bcm/bcm_kona_smc_asm.S b/trunk/arch/arm/mach-bcm/bcm_kona_smc_asm.S
deleted file mode 100644
index a1608480d60d..000000000000
--- a/trunk/arch/arm/mach-bcm/bcm_kona_smc_asm.S
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (C) 2013 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include
-#include "bcm_kona_smc.h"
-
-/*
- * int bcm_kona_smc_asm(u32 service_id, u32 buffer_addr)
- */
-
-ENTRY(bcm_kona_smc_asm)
- stmfd sp!, {r4-r12, lr}
- mov r4, r0 @ service_id
- mov r5, #3 @ Keep IRQ and FIQ off in SM
- /*
- * Since interrupts are disabled in the open mode, we must keep
- * interrupts disabled in secure mode by setting R5=0x3. If interrupts
- * are enabled in open mode, we can set R5=0x0 to allow interrupts in
- * secure mode. If we did this, the secure monitor would return back
- * control to the open mode to handle the interrupt prior to completing
- * the secure service. If this happened, R12 would not be
- * SEC_EXIT_NORMAL and we would need to call SMC again after resetting
- * R5 (it gets clobbered by the secure monitor) and setting R4 to
- * SSAPI_RET_FROM_INT_SERV to indicate that we want the secure monitor
- * to finish up the previous uncompleted secure service.
- */
- mov r6, r1 @ buffer_addr
- smc #0
- /* Check r12 for SEC_EXIT_NORMAL here if interrupts are enabled */
- ldmfd sp!, {r4-r12, pc}
-ENDPROC(bcm_kona_smc_asm)
diff --git a/trunk/arch/arm/mach-bcm/board_bcm.c b/trunk/arch/arm/mach-bcm/board_bcm.c
index 22e8421b1df3..259593540477 100644
--- a/trunk/arch/arm/mach-bcm/board_bcm.c
+++ b/trunk/arch/arm/mach-bcm/board_bcm.c
@@ -20,35 +20,12 @@
#include
#include
-#include
-#include "bcm_kona_smc.h"
-
-static int __init kona_l2_cache_init(void)
-{
- if (!IS_ENABLED(CONFIG_CACHE_L2X0))
- return 0;
-
- bcm_kona_smc(SSAPI_ENABLE_L2_CACHE, 0, 0, 0, 0);
-
- /*
- * The aux_val and aux_mask have no effect since L2 cache is already
- * enabled. Pass 0s for aux_val and 1s for aux_mask for default value.
- */
- l2x0_of_init(0, ~0);
-
- return 0;
-}
-
static void __init board_init(void)
{
of_platform_populate(NULL, of_default_bus_match_table, NULL,
&platform_bus);
-
- bcm_kona_smc_init();
-
- kona_l2_cache_init();
}
static const char * const bcm11351_dt_compat[] = { "bcm,bcm11351", NULL, };
diff --git a/trunk/arch/arm/mach-davinci/board-da830-evm.c b/trunk/arch/arm/mach-davinci/board-da830-evm.c
index 1332de8c52c9..12e6f756361d 100644
--- a/trunk/arch/arm/mach-davinci/board-da830-evm.c
+++ b/trunk/arch/arm/mach-davinci/board-da830-evm.c
@@ -297,7 +297,11 @@ static const short da830_evm_emif25_pins[] = {
-1
};
-#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
+#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
+#define HAS_MMC 1
+#else
+#define HAS_MMC 0
+#endif
#ifdef CONFIG_DA830_UI_NAND
static struct mtd_partition da830_evm_nand_partitions[] = {
diff --git a/trunk/arch/arm/mach-davinci/board-da850-evm.c b/trunk/arch/arm/mach-davinci/board-da850-evm.c
index 8a24b6c6339f..dcc8710936a5 100644
--- a/trunk/arch/arm/mach-davinci/board-da850-evm.c
+++ b/trunk/arch/arm/mach-davinci/board-da850-evm.c
@@ -335,7 +335,12 @@ static const short da850_evm_nor_pins[] = {
-1
};
-#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI)
+#if defined(CONFIG_MMC_DAVINCI) || \
+ defined(CONFIG_MMC_DAVINCI_MODULE)
+#define HAS_MMC 1
+#else
+#define HAS_MMC 0
+#endif
static inline void da850_evm_setup_nor_nand(void)
{
@@ -396,7 +401,7 @@ enum da850_evm_ui_exp_pins {
DA850_EVM_UI_EXP_PB1,
};
-static const char * const da850_evm_ui_exp[] = {
+static const char const *da850_evm_ui_exp[] = {
[DA850_EVM_UI_EXP_SEL_C] = "sel_c",
[DA850_EVM_UI_EXP_SEL_B] = "sel_b",
[DA850_EVM_UI_EXP_SEL_A] = "sel_a",
@@ -560,7 +565,7 @@ enum da850_evm_bb_exp_pins {
DA850_EVM_BB_EXP_USER_SW8
};
-static const char * const da850_evm_bb_exp[] = {
+static const char const *da850_evm_bb_exp[] = {
[DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en",
[DA850_EVM_BB_EXP_SW_RST] = "sw_rst",
[DA850_EVM_BB_EXP_TP_23] = "tp_23",
@@ -1572,11 +1577,6 @@ static __init void da850_evm_init(void)
pr_warn("%s: SATA registration failed: %d\n", __func__, ret);
da850_evm_setup_mac_addr();
-
- ret = da8xx_register_rproc();
- if (ret)
- pr_warn("%s: dsp/rproc registration failed: %d\n",
- __func__, ret);
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
@@ -1604,5 +1604,4 @@ MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM")
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = da8xx_restart,
- .reserve = da8xx_rproc_reserve_cma,
MACHINE_END
diff --git a/trunk/arch/arm/mach-davinci/board-dm644x-evm.c b/trunk/arch/arm/mach-davinci/board-dm644x-evm.c
index a33686a6fbb2..e62108fd7926 100644
--- a/trunk/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/trunk/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -749,11 +749,26 @@ static int davinci_phy_fixup(struct phy_device *phydev)
return 0;
}
-#define HAS_ATA IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
-
-#define HAS_NOR IS_ENABLED(CONFIG_MTD_PHYSMAP)
-
-#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
+ defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+#define HAS_ATA 1
+#else
+#define HAS_ATA 0
+#endif
+
+#if defined(CONFIG_MTD_PHYSMAP) || \
+ defined(CONFIG_MTD_PHYSMAP_MODULE)
+#define HAS_NOR 1
+#else
+#define HAS_NOR 0
+#endif
+
+#if defined(CONFIG_MTD_NAND_DAVINCI) || \
+ defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
+#define HAS_NAND 1
+#else
+#define HAS_NAND 0
+#endif
static __init void davinci_evm_init(void)
{
diff --git a/trunk/arch/arm/mach-davinci/board-dm646x-evm.c b/trunk/arch/arm/mach-davinci/board-dm646x-evm.c
index fbb8e5ab1dc1..fc4871ac1c2c 100644
--- a/trunk/arch/arm/mach-davinci/board-dm646x-evm.c
+++ b/trunk/arch/arm/mach-davinci/board-dm646x-evm.c
@@ -117,7 +117,12 @@ static struct platform_device davinci_nand_device = {
},
};
-#define HAS_ATA IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
+ defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+#define HAS_ATA 1
+#else
+#define HAS_ATA 0
+#endif
/* CPLD Register 0 bits to control ATA */
#define DM646X_EVM_ATA_RST BIT(0)
diff --git a/trunk/arch/arm/mach-davinci/board-neuros-osd2.c b/trunk/arch/arm/mach-davinci/board-neuros-osd2.c
index 2bc112adf565..b70e83c03bed 100644
--- a/trunk/arch/arm/mach-davinci/board-neuros-osd2.c
+++ b/trunk/arch/arm/mach-davinci/board-neuros-osd2.c
@@ -166,9 +166,20 @@ static struct davinci_mmc_config davinci_ntosd2_mmc_config = {
.wires = 4,
};
-#define HAS_ATA IS_ENABLED(CONFIG_BLK_DEV_PALMCHIP_BK3710)
-#define HAS_NAND IS_ENABLED(CONFIG_MTD_NAND_DAVINCI)
+#if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
+ defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
+#define HAS_ATA 1
+#else
+#define HAS_ATA 0
+#endif
+
+#if defined(CONFIG_MTD_NAND_DAVINCI) || \
+ defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
+#define HAS_NAND 1
+#else
+#define HAS_NAND 0
+#endif
static __init void davinci_ntosd2_init(void)
{
diff --git a/trunk/arch/arm/mach-davinci/board-omapl138-hawk.c b/trunk/arch/arm/mach-davinci/board-omapl138-hawk.c
index b8c20de10ca2..328dbd8a37f5 100644
--- a/trunk/arch/arm/mach-davinci/board-omapl138-hawk.c
+++ b/trunk/arch/arm/mach-davinci/board-omapl138-hawk.c
@@ -310,11 +310,6 @@ static __init void omapl138_hawk_init(void)
if (ret)
pr_warn("%s: watchdog registration failed: %d\n",
__func__, ret);
-
- ret = da8xx_register_rproc();
- if (ret)
- pr_warn("%s: dsp/rproc registration failed: %d\n",
- __func__, ret);
}
#ifdef CONFIG_SERIAL_8250_CONSOLE
@@ -342,5 +337,4 @@ MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard")
.init_late = davinci_init_late,
.dma_zone_size = SZ_128M,
.restart = da8xx_restart,
- .reserve = da8xx_rproc_reserve_cma,
MACHINE_END
diff --git a/trunk/arch/arm/mach-davinci/devices.c b/trunk/arch/arm/mach-davinci/devices.c
index a7068a3aa9d3..f6927df2dda8 100644
--- a/trunk/arch/arm/mach-davinci/devices.c
+++ b/trunk/arch/arm/mach-davinci/devices.c
@@ -119,7 +119,7 @@ void __init davinci_init_ide(void)
platform_device_register(&ide_device);
}
-#if IS_ENABLED(CONFIG_MMC_DAVINCI)
+#if defined(CONFIG_MMC_DAVINCI) || defined(CONFIG_MMC_DAVINCI_MODULE)
static u64 mmcsd0_dma_mask = DMA_BIT_MASK(32);
diff --git a/trunk/arch/arm/mach-davinci/usb.c b/trunk/arch/arm/mach-davinci/usb.c
index b0a6b522575f..2b4c648f99b6 100644
--- a/trunk/arch/arm/mach-davinci/usb.c
+++ b/trunk/arch/arm/mach-davinci/usb.c
@@ -18,7 +18,7 @@
#define DA8XX_USB0_BASE 0x01e00000
#define DA8XX_USB1_BASE 0x01e25000
-#if IS_ENABLED(CONFIG_USB_MUSB_HDRC)
+#if defined(CONFIG_USB_MUSB_HDRC) || defined(CONFIG_USB_MUSB_HDRC_MODULE)
static struct musb_hdrc_eps_bits musb_eps[] = {
{ "ep1_tx", 8, },
{ "ep1_rx", 8, },
diff --git a/trunk/arch/arm/mach-exynos/Kconfig b/trunk/arch/arm/mach-exynos/Kconfig
index d19edff0ea6e..f22f69e2d081 100644
--- a/trunk/arch/arm/mach-exynos/Kconfig
+++ b/trunk/arch/arm/mach-exynos/Kconfig
@@ -63,7 +63,6 @@ config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250"
default y
depends on ARCH_EXYNOS5
- select PM_GENERIC_DOMAINS if PM
select S5P_PM if PM
select S5P_SLEEP if PM
select S5P_DEV_MFC
@@ -84,6 +83,12 @@ config SOC_EXYNOS5440
help
Enable EXYNOS5440 SoC support
+config EXYNOS4_MCT
+ bool
+ default y
+ help
+ Use MCT (Multi Core Timer) as kernel timers
+
config EXYNOS_ATAGS
bool "ATAGS based boot for EXYNOS (deprecated)"
depends on !ARCH_MULTIPLATFORM
@@ -280,8 +285,8 @@ config MACH_UNIVERSAL_C210
select S5P_DEV_ONENAND
select S5P_DEV_TV
select S5P_GPIO_INT
+ select S5P_HRT
select S5P_SETUP_MIPIPHY
- select SAMSUNG_HRT
help
Machine support for Samsung Mobile Universal S5PC210 Reference
Board.
@@ -409,12 +414,10 @@ config MACH_EXYNOS4_DT
bool "Samsung Exynos4 Machine using device tree"
depends on ARCH_EXYNOS4
select ARM_AMBA
- select CLKSRC_OF
select CPU_EXYNOS4210
select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
select PINCTRL
select PINCTRL_EXYNOS
- select S5P_DEV_MFC
select USE_OF
help
Machine support for Samsung Exynos4 machine with device tree enabled.
@@ -427,7 +430,6 @@ config MACH_EXYNOS5_DT
default y
depends on ARCH_EXYNOS5
select ARM_AMBA
- select CLKSRC_OF
select USE_OF
help
Machine support for Samsung EXYNOS5 machine with device tree enabled.
diff --git a/trunk/arch/arm/mach-exynos/Makefile b/trunk/arch/arm/mach-exynos/Makefile
index b09b027178f3..435757e57bb4 100644
--- a/trunk/arch/arm/mach-exynos/Makefile
+++ b/trunk/arch/arm/mach-exynos/Makefile
@@ -13,6 +13,10 @@ obj- :=
# Core
obj-$(CONFIG_ARCH_EXYNOS) += common.o
+obj-$(CONFIG_ARCH_EXYNOS4) += clock-exynos4.o
+obj-$(CONFIG_CPU_EXYNOS4210) += clock-exynos4210.o
+obj-$(CONFIG_SOC_EXYNOS4212) += clock-exynos4212.o
+obj-$(CONFIG_SOC_EXYNOS5250) += clock-exynos5.o
obj-$(CONFIG_PM) += pm.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
@@ -22,13 +26,9 @@ obj-$(CONFIG_ARCH_EXYNOS) += pmu.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
-obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
-
-obj-$(CONFIG_ARCH_EXYNOS) += exynos-smc.o
-obj-$(CONFIG_ARCH_EXYNOS) += firmware.o
+obj-$(CONFIG_EXYNOS4_MCT) += mct.o
-plus_sec := $(call as-instr,.arch_extension sec,+sec)
-AFLAGS_exynos-smc.o :=-Wa,-march=armv7-a$(plus_sec)
+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
# machine support
diff --git a/trunk/arch/arm/mach-exynos/clock-exynos4.c b/trunk/arch/arm/mach-exynos/clock-exynos4.c
new file mode 100644
index 000000000000..8a8468d83c8c
--- /dev/null
+++ b/trunk/arch/arm/mach-exynos/clock-exynos4.c
@@ -0,0 +1,1601 @@
+/*
+ * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "common.h"
+#include "clock-exynos4.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos4_clock_save[] = {
+ SAVE_ITEM(EXYNOS4_CLKDIV_LEFTBUS),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_LEFTBUS),
+ SAVE_ITEM(EXYNOS4_CLKDIV_RIGHTBUS),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_RIGHTBUS),
+ SAVE_ITEM(EXYNOS4_CLKSRC_TOP0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_TOP1),
+ SAVE_ITEM(EXYNOS4_CLKSRC_CAM),
+ SAVE_ITEM(EXYNOS4_CLKSRC_TV),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MFC),
+ SAVE_ITEM(EXYNOS4_CLKSRC_G3D),
+ SAVE_ITEM(EXYNOS4_CLKSRC_LCD0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MAUDIO),
+ SAVE_ITEM(EXYNOS4_CLKSRC_FSYS),
+ SAVE_ITEM(EXYNOS4_CLKSRC_PERIL0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_PERIL1),
+ SAVE_ITEM(EXYNOS4_CLKDIV_CAM),
+ SAVE_ITEM(EXYNOS4_CLKDIV_TV),
+ SAVE_ITEM(EXYNOS4_CLKDIV_MFC),
+ SAVE_ITEM(EXYNOS4_CLKDIV_G3D),
+ SAVE_ITEM(EXYNOS4_CLKDIV_LCD0),
+ SAVE_ITEM(EXYNOS4_CLKDIV_MAUDIO),
+ SAVE_ITEM(EXYNOS4_CLKDIV_FSYS0),
+ SAVE_ITEM(EXYNOS4_CLKDIV_FSYS1),
+ SAVE_ITEM(EXYNOS4_CLKDIV_FSYS2),
+ SAVE_ITEM(EXYNOS4_CLKDIV_FSYS3),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL0),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL1),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL2),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL3),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL4),
+ SAVE_ITEM(EXYNOS4_CLKDIV_PERIL5),
+ SAVE_ITEM(EXYNOS4_CLKDIV_TOP),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TOP),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_CAM),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_TV),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_LCD0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_MAUDIO),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_FSYS),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL0),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_PERIL1),
+ SAVE_ITEM(EXYNOS4_CLKDIV2_RATIO),
+ SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCAM),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_CAM),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_TV),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_MFC),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_G3D),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_LCD0),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_FSYS),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_GPS),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_PERIL),
+ SAVE_ITEM(EXYNOS4_CLKGATE_BLOCK),
+ SAVE_ITEM(EXYNOS4_CLKSRC_MASK_DMC),
+ SAVE_ITEM(EXYNOS4_CLKSRC_DMC),
+ SAVE_ITEM(EXYNOS4_CLKDIV_DMC0),
+ SAVE_ITEM(EXYNOS4_CLKDIV_DMC1),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_DMC),
+ SAVE_ITEM(EXYNOS4_CLKSRC_CPU),
+ SAVE_ITEM(EXYNOS4_CLKDIV_CPU),
+ SAVE_ITEM(EXYNOS4_CLKDIV_CPU + 0x4),
+ SAVE_ITEM(EXYNOS4_CLKGATE_SCLKCPU),
+ SAVE_ITEM(EXYNOS4_CLKGATE_IP_CPU),
+};
+#endif
+
+static struct clk exynos4_clk_sclk_hdmi27m = {
+ .name = "sclk_hdmi27m",
+ .rate = 27000000,
+};
+
+static struct clk exynos4_clk_sclk_hdmiphy = {
+ .name = "sclk_hdmiphy",
+};
+
+static struct clk exynos4_clk_sclk_usbphy0 = {
+ .name = "sclk_usbphy0",
+ .rate = 27000000,
+};
+
+static struct clk exynos4_clk_sclk_usbphy1 = {
+ .name = "sclk_usbphy1",
+};
+
+static struct clk dummy_apb_pclk = {
+ .name = "apb_pclk",
+ .id = -1,
+};
+
+static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_CAM, clk, enable);
+}
+
+static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_LCD0, clk, enable);
+}
+
+int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL0, clk, enable);
+}
+
+static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_PERIL1, clk, enable);
+}
+
+static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos4_clksrc_mask_tv_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKSRC_MASK_TV, clk, enable);
+}
+
+static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_CAM, clk, enable);
+}
+
+static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_TV, clk, enable);
+}
+
+int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_IMAGE, clk, enable);
+}
+
+static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_LCD0, clk, enable);
+}
+
+int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4210_CLKGATE_IP_LCD1, clk, enable);
+}
+
+int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIL, clk, enable);
+}
+
+static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_PERIR, clk, enable);
+}
+
+int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_DMC, clk, enable);
+}
+
+static int exynos4_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+static int exynos4_clk_dac_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_DAC_PHY_CONTROL, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos4_clk_mout_apll = {
+ .clk = {
+ .name = "mout_apll",
+ },
+ .sources = &clk_src_apll,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_apll = {
+ .clk = {
+ .name = "sclk_apll",
+ .parent = &exynos4_clk_mout_apll.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_mout_epll = {
+ .clk = {
+ .name = "mout_epll",
+ },
+ .sources = &clk_src_epll,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 4, .size = 1 },
+};
+
+struct clksrc_clk exynos4_clk_mout_mpll = {
+ .clk = {
+ .name = "mout_mpll",
+ },
+ .sources = &clk_src_mpll,
+
+ /* reg_src will be added in each SoCs' clock */
+};
+
+static struct clk *exynos4_clkset_moutcore_list[] = {
+ [0] = &exynos4_clk_mout_apll.clk,
+ [1] = &exynos4_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_moutcore = {
+ .sources = exynos4_clkset_moutcore_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_moutcore_list),
+};
+
+static struct clksrc_clk exynos4_clk_moutcore = {
+ .clk = {
+ .name = "moutcore",
+ },
+ .sources = &exynos4_clkset_moutcore,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_coreclk = {
+ .clk = {
+ .name = "core_clk",
+ .parent = &exynos4_clk_moutcore.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_armclk = {
+ .clk = {
+ .name = "armclk",
+ .parent = &exynos4_clk_coreclk.clk,
+ },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem0 = {
+ .clk = {
+ .name = "aclk_corem0",
+ .parent = &exynos4_clk_coreclk.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cores = {
+ .clk = {
+ .name = "aclk_cores",
+ .parent = &exynos4_clk_coreclk.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 4, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corem1 = {
+ .clk = {
+ .name = "aclk_corem1",
+ .parent = &exynos4_clk_coreclk.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_periphclk = {
+ .clk = {
+ .name = "periphclk",
+ .parent = &exynos4_clk_coreclk.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CPU, .shift = 12, .size = 3 },
+};
+
+/* Core list of CMU_CORE side */
+
+static struct clk *exynos4_clkset_corebus_list[] = {
+ [0] = &exynos4_clk_mout_mpll.clk,
+ [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_mout_corebus = {
+ .sources = exynos4_clkset_corebus_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_corebus_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_corebus = {
+ .clk = {
+ .name = "mout_corebus",
+ },
+ .sources = &exynos4_clkset_mout_corebus,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dmc = {
+ .clk = {
+ .name = "sclk_dmc",
+ .parent = &exynos4_clk_mout_corebus.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_cored = {
+ .clk = {
+ .name = "aclk_cored",
+ .parent = &exynos4_clk_sclk_dmc.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_corep = {
+ .clk = {
+ .name = "aclk_corep",
+ .parent = &exynos4_clk_aclk_cored.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_acp = {
+ .clk = {
+ .name = "aclk_acp",
+ .parent = &exynos4_clk_mout_corebus.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_pclk_acp = {
+ .clk = {
+ .name = "pclk_acp",
+ .parent = &exynos4_clk_aclk_acp.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC0, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+struct clk *exynos4_clkset_aclk_top_list[] = {
+ [0] = &exynos4_clk_mout_mpll.clk,
+ [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_aclk = {
+ .sources = exynos4_clkset_aclk_top_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos4_clk_aclk_200 = {
+ .clk = {
+ .name = "aclk_200",
+ },
+ .sources = &exynos4_clkset_aclk,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 12, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_100 = {
+ .clk = {
+ .name = "aclk_100",
+ },
+ .sources = &exynos4_clkset_aclk,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 16, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_aclk_160 = {
+ .clk = {
+ .name = "aclk_160",
+ },
+ .sources = &exynos4_clkset_aclk,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 20, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 8, .size = 3 },
+};
+
+struct clksrc_clk exynos4_clk_aclk_133 = {
+ .clk = {
+ .name = "aclk_133",
+ },
+ .sources = &exynos4_clkset_aclk,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 24, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_TOP, .shift = 12, .size = 3 },
+};
+
+static struct clk *exynos4_clkset_vpllsrc_list[] = {
+ [0] = &clk_fin_vpll,
+ [1] = &exynos4_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos4_clkset_vpllsrc = {
+ .sources = exynos4_clkset_vpllsrc_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos4_clk_vpllsrc = {
+ .clk = {
+ .name = "vpll_src",
+ .enable = exynos4_clksrc_mask_top_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_vpllsrc,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP1, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_vpll_list[] = {
+ [0] = &exynos4_clk_vpllsrc.clk,
+ [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_vpll = {
+ .sources = exynos4_clkset_sclk_vpll_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_vpll = {
+ .clk = {
+ .name = "sclk_vpll",
+ },
+ .sources = &exynos4_clkset_sclk_vpll,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TOP0, .shift = 8, .size = 1 },
+};
+
+static struct clk exynos4_init_clocks_off[] = {
+ {
+ .name = "timers",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1<<24),
+ }, {
+ .name = "csis",
+ .devname = "s5p-mipi-csis.0",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "csis",
+ .devname = "s5p-mipi-csis.1",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "jpeg",
+ .id = 0,
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "fimc",
+ .devname = "exynos4-fimc.0",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "fimc",
+ .devname = "exynos4-fimc.1",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "fimc",
+ .devname = "exynos4-fimc.2",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "fimc",
+ .devname = "exynos4-fimc.3",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "tsi",
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.0",
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.1",
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.2",
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "hsmmc",
+ .devname = "exynos4-sdhci.3",
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "biu",
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "onenand",
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 15),
+ }, {
+ .name = "nfcon",
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "dac",
+ .devname = "s5p-sdo",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "mixer",
+ .devname = "s5p-mixer",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "vp",
+ .devname = "s5p-mixer",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "hdmi",
+ .devname = "exynos4-hdmi",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "hdmiphy",
+ .devname = "exynos4-hdmi",
+ .enable = exynos4_clk_hdmiphy_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "dacphy",
+ .devname = "s5p-sdo",
+ .enable = exynos4_clk_dac_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "adc",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 15),
+ }, {
+ .name = "tmu_apbif",
+ .enable = exynos4_clk_ip_perir_ctrl,
+ .ctrlbit = (1 << 17),
+ }, {
+ .name = "keypad",
+ .enable = exynos4_clk_ip_perir_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "rtc",
+ .enable = exynos4_clk_ip_perir_ctrl,
+ .ctrlbit = (1 << 15),
+ }, {
+ .name = "watchdog",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_perir_ctrl,
+ .ctrlbit = (1 << 14),
+ }, {
+ .name = "usbhost",
+ .enable = exynos4_clk_ip_fsys_ctrl ,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "otg",
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 13),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.0",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.1",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 17),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.2",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 18),
+ }, {
+ .name = "iis",
+ .devname = "samsung-i2s.1",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 20),
+ }, {
+ .name = "iis",
+ .devname = "samsung-i2s.2",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 21),
+ }, {
+ .name = "pcm",
+ .devname = "samsung-pcm.1",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 22),
+ }, {
+ .name = "pcm",
+ .devname = "samsung-pcm.2",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 23),
+ }, {
+ .name = "slimbus",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 25),
+ }, {
+ .name = "spdif",
+ .devname = "samsung-spdif",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 26),
+ }, {
+ .name = "ac97",
+ .devname = "samsung-ac97",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 27),
+ }, {
+ .name = "mfc",
+ .devname = "s5p-mfc",
+ .enable = exynos4_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.0",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.1",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.2",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.3",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.4",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.5",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.6",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.7",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 13),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-hdmiphy-i2c",
+ .parent = &exynos4_clk_aclk_100.clk,
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 14),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.0",
+ .enable = exynos4_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.1",
+ .enable = exynos4_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.2",
+ .enable = exynos4_clk_ip_tv_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.3",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.4",
+ .enable = exynos4_clk_ip_image_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.5",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.6",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.7",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.8",
+ .enable = exynos4_clk_ip_cam_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.10",
+ .enable = exynos4_clk_ip_lcd0_ctrl,
+ .ctrlbit = (1 << 4),
+ }
+};
+
+static struct clk exynos4_init_clocks_on[] = {
+ {
+ .name = "uart",
+ .devname = "s5pv210-uart.0",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.1",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.2",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.3",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.4",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.5",
+ .enable = exynos4_clk_ip_peril_ctrl,
+ .ctrlbit = (1 << 5),
+ }
+};
+
+static struct clk exynos4_clk_pdma0 = {
+ .name = "dma",
+ .devname = "dma-pl330.0",
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+};
+
+static struct clk exynos4_clk_pdma1 = {
+ .name = "dma",
+ .devname = "dma-pl330.1",
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 1),
+};
+
+static struct clk exynos4_clk_mdma1 = {
+ .name = "dma",
+ .devname = "dma-pl330.2",
+ .enable = exynos4_clk_ip_image_ctrl,
+ .ctrlbit = ((1 << 8) | (1 << 5) | (1 << 2)),
+};
+
+static struct clk exynos4_clk_fimd0 = {
+ .name = "fimd",
+ .devname = "exynos4-fb.0",
+ .enable = exynos4_clk_ip_lcd0_ctrl,
+ .ctrlbit = (1 << 0),
+};
+
+struct clk *exynos4_clkset_group_list[] = {
+ [0] = &clk_ext_xtal_mux,
+ [1] = &clk_xusbxti,
+ [2] = &exynos4_clk_sclk_hdmi27m,
+ [3] = &exynos4_clk_sclk_usbphy0,
+ [4] = &exynos4_clk_sclk_usbphy1,
+ [5] = &exynos4_clk_sclk_hdmiphy,
+ [6] = &exynos4_clk_mout_mpll.clk,
+ [7] = &exynos4_clk_mout_epll.clk,
+ [8] = &exynos4_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_group = {
+ .sources = exynos4_clkset_group_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_group_list),
+};
+
+static struct clk *exynos4_clkset_mout_g2d0_list[] = {
+ [0] = &exynos4_clk_mout_mpll.clk,
+ [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_mout_g2d0 = {
+ .sources = exynos4_clkset_mout_g2d0_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d0_list),
+};
+
+static struct clk *exynos4_clkset_mout_g2d1_list[] = {
+ [0] = &exynos4_clk_mout_epll.clk,
+ [1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+struct clksrc_sources exynos4_clkset_mout_g2d1 = {
+ .sources = exynos4_clkset_mout_g2d1_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_g2d1_list),
+};
+
+static struct clk *exynos4_clkset_mout_mfc0_list[] = {
+ [0] = &exynos4_clk_mout_mpll.clk,
+ [1] = &exynos4_clk_sclk_apll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc0 = {
+ .sources = exynos4_clkset_mout_mfc0_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc0_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc0 = {
+ .clk = {
+ .name = "mout_mfc0",
+ },
+ .sources = &exynos4_clkset_mout_mfc0,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc1_list[] = {
+ [0] = &exynos4_clk_mout_epll.clk,
+ [1] = &exynos4_clk_sclk_vpll.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc1 = {
+ .sources = exynos4_clkset_mout_mfc1_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc1_list),
+};
+
+static struct clksrc_clk exynos4_clk_mout_mfc1 = {
+ .clk = {
+ .name = "mout_mfc1",
+ },
+ .sources = &exynos4_clkset_mout_mfc1,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_mout_mfc_list[] = {
+ [0] = &exynos4_clk_mout_mfc0.clk,
+ [1] = &exynos4_clk_mout_mfc1.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_mout_mfc = {
+ .sources = exynos4_clkset_mout_mfc_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_mout_mfc_list),
+};
+
+static struct clk *exynos4_clkset_sclk_dac_list[] = {
+ [0] = &exynos4_clk_sclk_vpll.clk,
+ [1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_dac = {
+ .sources = exynos4_clkset_sclk_dac_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_dac_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_dac = {
+ .clk = {
+ .name = "sclk_dac",
+ .enable = exynos4_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &exynos4_clkset_sclk_dac,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_pixel = {
+ .clk = {
+ .name = "sclk_pixel",
+ .parent = &exynos4_clk_sclk_vpll.clk,
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_TV, .shift = 0, .size = 4 },
+};
+
+static struct clk *exynos4_clkset_sclk_hdmi_list[] = {
+ [0] = &exynos4_clk_sclk_pixel.clk,
+ [1] = &exynos4_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_hdmi = {
+ .sources = exynos4_clkset_sclk_hdmi_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_hdmi = {
+ .clk = {
+ .name = "sclk_hdmi",
+ .enable = exynos4_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_sclk_hdmi,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos4_clkset_sclk_mixer_list[] = {
+ [0] = &exynos4_clk_sclk_dac.clk,
+ [1] = &exynos4_clk_sclk_hdmi.clk,
+};
+
+static struct clksrc_sources exynos4_clkset_sclk_mixer = {
+ .sources = exynos4_clkset_sclk_mixer_list,
+ .nr_sources = ARRAY_SIZE(exynos4_clkset_sclk_mixer_list),
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mixer = {
+ .clk = {
+ .name = "sclk_mixer",
+ .enable = exynos4_clksrc_mask_tv_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &exynos4_clkset_sclk_mixer,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_TV, .shift = 4, .size = 1 },
+};
+
+static struct clksrc_clk *exynos4_sclk_tv[] = {
+ &exynos4_clk_sclk_dac,
+ &exynos4_clk_sclk_pixel,
+ &exynos4_clk_sclk_hdmi,
+ &exynos4_clk_sclk_mixer,
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc0 = {
+ .clk = {
+ .name = "dout_mmc0",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc1 = {
+ .clk = {
+ .name = "dout_mmc1",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 4, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc2 = {
+ .clk = {
+ .name = "dout_mmc2",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 8, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc3 = {
+ .clk = {
+ .name = "dout_mmc3",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_dout_mmc4 = {
+ .clk = {
+ .name = "dout_mmc4",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clksrcs[] = {
+ {
+ .clk = {
+ .name = "sclk_pwm",
+ .enable = exynos4_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL3, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_csis",
+ .devname = "s5p-mipi-csis.0",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 24, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_csis",
+ .devname = "s5p-mipi-csis.1",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 28),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 28, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 28, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam0",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 16, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam1",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .devname = "exynos4-fimc.0",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .devname = "exynos4-fimc.1",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 4, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 4, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .devname = "exynos4-fimc.2",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 8, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 8, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimc",
+ .devname = "exynos4-fimc.3",
+ .enable = exynos4_clksrc_mask_cam_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CAM, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_CAM, .shift = 12, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimd",
+ .devname = "exynos4-fb.0",
+ .enable = exynos4_clksrc_mask_lcd0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_LCD0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_LCD0, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_mfc",
+ .devname = "s5p-mfc",
+ },
+ .sources = &exynos4_clkset_mout_mfc,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_MFC, .shift = 8, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_MFC, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "ciu",
+ .parent = &exynos4_clk_dout_mmc4.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS3, .shift = 8, .size = 8 },
+ }
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart0 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.0",
+ .enable = exynos4_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart1 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.1",
+ .enable = exynos4_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 4, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart2 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.2",
+ .enable = exynos4_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 8, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_uart3 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.3",
+ .enable = exynos4_clksrc_mask_peril0_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL0, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.0",
+ .parent = &exynos4_clk_dout_mmc0.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.1",
+ .parent = &exynos4_clk_dout_mmc1.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.2",
+ .parent = &exynos4_clk_dout_mmc2.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
+ .clk = {
+ .name = "sclk_mmc",
+ .devname = "exynos4-sdhci.3",
+ .parent = &exynos4_clk_dout_mmc3.clk,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi0 = {
+ .clk = {
+ .name = "mdout_spi",
+ .devname = "exynos4210-spi.0",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi1 = {
+ .clk = {
+ .name = "mdout_spi",
+ .devname = "exynos4210-spi.1",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_mdout_spi2 = {
+ .clk = {
+ .name = "mdout_spi",
+ .devname = "exynos4210-spi.2",
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_PERIL1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos4_clk_mdout_spi0.clk,
+ .enable = exynos4_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos4_clk_mdout_spi1.clk,
+ .enable = exynos4_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos4_clk_sclk_spi2 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos4_clk_mdout_spi2.clk,
+ .enable = exynos4_clksrc_mask_peril1_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_PERIL2, .shift = 8, .size = 8 },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos4_sysclks[] = {
+ &exynos4_clk_mout_apll,
+ &exynos4_clk_sclk_apll,
+ &exynos4_clk_mout_epll,
+ &exynos4_clk_mout_mpll,
+ &exynos4_clk_moutcore,
+ &exynos4_clk_coreclk,
+ &exynos4_clk_armclk,
+ &exynos4_clk_aclk_corem0,
+ &exynos4_clk_aclk_cores,
+ &exynos4_clk_aclk_corem1,
+ &exynos4_clk_periphclk,
+ &exynos4_clk_mout_corebus,
+ &exynos4_clk_sclk_dmc,
+ &exynos4_clk_aclk_cored,
+ &exynos4_clk_aclk_corep,
+ &exynos4_clk_aclk_acp,
+ &exynos4_clk_pclk_acp,
+ &exynos4_clk_vpllsrc,
+ &exynos4_clk_sclk_vpll,
+ &exynos4_clk_aclk_200,
+ &exynos4_clk_aclk_100,
+ &exynos4_clk_aclk_160,
+ &exynos4_clk_aclk_133,
+ &exynos4_clk_dout_mmc0,
+ &exynos4_clk_dout_mmc1,
+ &exynos4_clk_dout_mmc2,
+ &exynos4_clk_dout_mmc3,
+ &exynos4_clk_dout_mmc4,
+ &exynos4_clk_mout_mfc0,
+ &exynos4_clk_mout_mfc1,
+};
+
+static struct clk *exynos4_clk_cdev[] = {
+ &exynos4_clk_pdma0,
+ &exynos4_clk_pdma1,
+ &exynos4_clk_mdma1,
+ &exynos4_clk_fimd0,
+};
+
+static struct clksrc_clk *exynos4_clksrc_cdev[] = {
+ &exynos4_clk_sclk_uart0,
+ &exynos4_clk_sclk_uart1,
+ &exynos4_clk_sclk_uart2,
+ &exynos4_clk_sclk_uart3,
+ &exynos4_clk_sclk_mmc0,
+ &exynos4_clk_sclk_mmc1,
+ &exynos4_clk_sclk_mmc2,
+ &exynos4_clk_sclk_mmc3,
+ &exynos4_clk_sclk_spi0,
+ &exynos4_clk_sclk_spi1,
+ &exynos4_clk_sclk_spi2,
+ &exynos4_clk_mdout_spi0,
+ &exynos4_clk_mdout_spi1,
+ &exynos4_clk_mdout_spi2,
+};
+
+static struct clk_lookup exynos4_clk_lookup[] = {
+ CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos4_clk_sclk_uart0.clk),
+ CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
+ CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
+ CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
+ CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
+ CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
+ CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
+ CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
+ CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
+ CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
+ CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
+ CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos4_clk_mdma1),
+ CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos4_clk_sclk_spi0.clk),
+ CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos4_clk_sclk_spi1.clk),
+ CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos4_clk_sclk_spi2.clk),
+};
+
+static int xtal_rate;
+
+static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
+{
+ if (soc_is_exynos4210())
+ return s5p_get_pll45xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0),
+ pll_4508);
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
+ return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS4_APLL_CON0));
+ else
+ return 0;
+}
+
+static struct clk_ops exynos4_fout_apll_ops = {
+ .get_rate = exynos4_fout_apll_get_rate,
+};
+
+static u32 exynos4_vpll_div[][8] = {
+ { 54000000, 3, 53, 3, 1024, 0, 17, 0 },
+ { 108000000, 3, 53, 2, 1024, 0, 17, 0 },
+};
+
+static unsigned long exynos4_vpll_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+
+static int exynos4_vpll_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned int vpll_con0, vpll_con1 = 0;
+ unsigned int i;
+
+ /* Return if nothing changed */
+ if (clk->rate == rate)
+ return 0;
+
+ vpll_con0 = __raw_readl(EXYNOS4_VPLL_CON0);
+ vpll_con0 &= ~(0x1 << 27 | \
+ PLL90XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
+ PLL90XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+ PLL90XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+ vpll_con1 = __raw_readl(EXYNOS4_VPLL_CON1);
+ vpll_con1 &= ~(PLL46XX_MRR_MASK << PLL46XX_MRR_SHIFT | \
+ PLL46XX_MFR_MASK << PLL46XX_MFR_SHIFT | \
+ PLL4650C_KDIV_MASK << PLL46XX_KDIV_SHIFT);
+
+ for (i = 0; i < ARRAY_SIZE(exynos4_vpll_div); i++) {
+ if (exynos4_vpll_div[i][0] == rate) {
+ vpll_con0 |= exynos4_vpll_div[i][1] << PLL46XX_PDIV_SHIFT;
+ vpll_con0 |= exynos4_vpll_div[i][2] << PLL46XX_MDIV_SHIFT;
+ vpll_con0 |= exynos4_vpll_div[i][3] << PLL46XX_SDIV_SHIFT;
+ vpll_con1 |= exynos4_vpll_div[i][4] << PLL46XX_KDIV_SHIFT;
+ vpll_con1 |= exynos4_vpll_div[i][5] << PLL46XX_MFR_SHIFT;
+ vpll_con1 |= exynos4_vpll_div[i][6] << PLL46XX_MRR_SHIFT;
+ vpll_con0 |= exynos4_vpll_div[i][7] << 27;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(exynos4_vpll_div)) {
+ printk(KERN_ERR "%s: Invalid Clock VPLL Frequency\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ __raw_writel(vpll_con0, EXYNOS4_VPLL_CON0);
+ __raw_writel(vpll_con1, EXYNOS4_VPLL_CON1);
+
+ /* Wait for VPLL lock */
+ while (!(__raw_readl(EXYNOS4_VPLL_CON0) & (1 << PLL46XX_LOCKED_SHIFT)))
+ continue;
+
+ clk->rate = rate;
+ return 0;
+}
+
+static struct clk_ops exynos4_vpll_ops = {
+ .get_rate = exynos4_vpll_get_rate,
+ .set_rate = exynos4_vpll_set_rate,
+};
+
+void __init_or_cpufreq exynos4_setup_clocks(void)
+{
+ struct clk *xtal_clk;
+ unsigned long apll = 0;
+ unsigned long mpll = 0;
+ unsigned long epll = 0;
+ unsigned long vpll = 0;
+ unsigned long vpllsrc;
+ unsigned long xtal;
+ unsigned long armclk;
+ unsigned long sclk_dmc;
+ unsigned long aclk_200;
+ unsigned long aclk_100;
+ unsigned long aclk_160;
+ unsigned long aclk_133;
+ unsigned int ptr;
+
+ printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+ xtal_clk = clk_get(NULL, "xtal");
+ BUG_ON(IS_ERR(xtal_clk));
+
+ xtal = clk_get_rate(xtal_clk);
+
+ xtal_rate = xtal;
+
+ clk_put(xtal_clk);
+
+ printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+ if (soc_is_exynos4210()) {
+ apll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_APLL_CON0),
+ pll_4508);
+ mpll = s5p_get_pll45xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0),
+ pll_4508);
+ epll = s5p_get_pll46xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+ __raw_readl(EXYNOS4_EPLL_CON1), pll_4600);
+
+ vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+ vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+ __raw_readl(EXYNOS4_VPLL_CON1), pll_4650c);
+ } else if (soc_is_exynos4212() || soc_is_exynos4412()) {
+ apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_APLL_CON0));
+ mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS4_MPLL_CON0));
+ epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS4_EPLL_CON0),
+ __raw_readl(EXYNOS4_EPLL_CON1));
+
+ vpllsrc = clk_get_rate(&exynos4_clk_vpllsrc.clk);
+ vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS4_VPLL_CON0),
+ __raw_readl(EXYNOS4_VPLL_CON1));
+ } else {
+ /* nothing */
+ }
+
+ clk_fout_apll.ops = &exynos4_fout_apll_ops;
+ clk_fout_mpll.rate = mpll;
+ clk_fout_epll.rate = epll;
+ clk_fout_vpll.ops = &exynos4_vpll_ops;
+ clk_fout_vpll.rate = vpll;
+
+ printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
+ apll, mpll, epll, vpll);
+
+ armclk = clk_get_rate(&exynos4_clk_armclk.clk);
+ sclk_dmc = clk_get_rate(&exynos4_clk_sclk_dmc.clk);
+
+ aclk_200 = clk_get_rate(&exynos4_clk_aclk_200.clk);
+ aclk_100 = clk_get_rate(&exynos4_clk_aclk_100.clk);
+ aclk_160 = clk_get_rate(&exynos4_clk_aclk_160.clk);
+ aclk_133 = clk_get_rate(&exynos4_clk_aclk_133.clk);
+
+ printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
+ "ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
+ armclk, sclk_dmc, aclk_200,
+ aclk_100, aclk_160, aclk_133);
+
+ clk_f.rate = armclk;
+ clk_h.rate = sclk_dmc;
+ clk_p.rate = aclk_100;
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrcs); ptr++)
+ s3c_set_clksrc(&exynos4_clksrcs[ptr], true);
+}
+
+static struct clk *exynos4_clks[] __initdata = {
+ &exynos4_clk_sclk_hdmi27m,
+ &exynos4_clk_sclk_hdmiphy,
+ &exynos4_clk_sclk_usbphy0,
+ &exynos4_clk_sclk_usbphy1,
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+ return 0;
+}
+
+static void exynos4_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos4_clock_save, ARRAY_SIZE(exynos4_clock_save));
+}
+
+#else
+#define exynos4_clock_suspend NULL
+#define exynos4_clock_resume NULL
+#endif
+
+static struct syscore_ops exynos4_clock_syscore_ops = {
+ .suspend = exynos4_clock_suspend,
+ .resume = exynos4_clock_resume,
+};
+
+void __init exynos4_register_clocks(void)
+{
+ int ptr;
+
+ s3c24xx_register_clocks(exynos4_clks, ARRAY_SIZE(exynos4_clks));
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sysclks); ptr++)
+ s3c_register_clksrc(exynos4_sysclks[ptr], 1);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos4_sclk_tv); ptr++)
+ s3c_register_clksrc(exynos4_sclk_tv[ptr], 1);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clksrc_cdev); ptr++)
+ s3c_register_clksrc(exynos4_clksrc_cdev[ptr], 1);
+
+ s3c_register_clksrc(exynos4_clksrcs, ARRAY_SIZE(exynos4_clksrcs));
+ s3c_register_clocks(exynos4_init_clocks_on, ARRAY_SIZE(exynos4_init_clocks_on));
+
+ s3c24xx_register_clocks(exynos4_clk_cdev, ARRAY_SIZE(exynos4_clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos4_clk_cdev); ptr++)
+ s3c_disable_clocks(exynos4_clk_cdev[ptr], 1);
+
+ s3c_register_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+ s3c_disable_clocks(exynos4_init_clocks_off, ARRAY_SIZE(exynos4_init_clocks_off));
+ clkdev_add_table(exynos4_clk_lookup, ARRAY_SIZE(exynos4_clk_lookup));
+
+ register_syscore_ops(&exynos4_clock_syscore_ops);
+ s3c24xx_register_clock(&dummy_apb_pclk);
+
+ s3c_pwmclk_init();
+}
diff --git a/trunk/arch/arm/mach-exynos/clock-exynos4.h b/trunk/arch/arm/mach-exynos/clock-exynos4.h
new file mode 100644
index 000000000000..bd12d5f8b63d
--- /dev/null
+++ b/trunk/arch/arm/mach-exynos/clock-exynos4.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Header file for exynos4 clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_CLOCK_H
+#define __ASM_ARCH_CLOCK_H __FILE__
+
+#include
+
+extern struct clksrc_clk exynos4_clk_aclk_133;
+extern struct clksrc_clk exynos4_clk_mout_mpll;
+
+extern struct clksrc_sources exynos4_clkset_mout_corebus;
+extern struct clksrc_sources exynos4_clkset_group;
+
+extern struct clk *exynos4_clkset_aclk_top_list[];
+extern struct clk *exynos4_clkset_group_list[];
+
+extern struct clksrc_sources exynos4_clkset_mout_g2d0;
+extern struct clksrc_sources exynos4_clkset_mout_g2d1;
+
+extern int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable);
+extern int exynos4_clk_ip_dmc_ctrl(struct clk *clk, int enable);
+
+#endif /* __ASM_ARCH_CLOCK_H */
diff --git a/trunk/arch/arm/mach-exynos/clock-exynos4210.c b/trunk/arch/arm/mach-exynos/clock-exynos4210.c
new file mode 100644
index 000000000000..19af9f783c56
--- /dev/null
+++ b/trunk/arch/arm/mach-exynos/clock-exynos4210.c
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4210 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "common.h"
+#include "clock-exynos4.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos4210_clock_save[] = {
+ SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+ SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+ SAVE_ITEM(EXYNOS4210_CLKSRC_LCD1),
+ SAVE_ITEM(EXYNOS4210_CLKDIV_LCD1),
+ SAVE_ITEM(EXYNOS4210_CLKSRC_MASK_LCD1),
+ SAVE_ITEM(EXYNOS4210_CLKGATE_IP_IMAGE),
+ SAVE_ITEM(EXYNOS4210_CLKGATE_IP_LCD1),
+ SAVE_ITEM(EXYNOS4210_CLKGATE_IP_PERIR),
+};
+#endif
+
+static struct clksrc_clk *sysclks[] = {
+ /* nothing here yet */
+};
+
+static struct clksrc_clk exynos4210_clk_mout_g2d0 = {
+ .clk = {
+ .name = "mout_g2d0",
+ },
+ .sources = &exynos4_clkset_mout_g2d0,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos4210_clk_mout_g2d1 = {
+ .clk = {
+ .name = "mout_g2d1",
+ },
+ .sources = &exynos4_clkset_mout_g2d1,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos4210_clkset_mout_g2d_list[] = {
+ [0] = &exynos4210_clk_mout_g2d0.clk,
+ [1] = &exynos4210_clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources exynos4210_clkset_mout_g2d = {
+ .sources = exynos4210_clkset_mout_g2d_list,
+ .nr_sources = ARRAY_SIZE(exynos4210_clkset_mout_g2d_list),
+};
+
+static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4210_CLKSRC_MASK_LCD1, clk, enable);
+}
+
+static struct clksrc_clk clksrcs[] = {
+ {
+ .clk = {
+ .name = "sclk_sata",
+ .id = -1,
+ .enable = exynos4_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &exynos4_clkset_mout_corebus,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_FSYS, .shift = 24, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimd",
+ .devname = "exynos4-fb.1",
+ .enable = exynos4_clksrc_mask_lcd1_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos4_clkset_group,
+ .reg_src = { .reg = EXYNOS4210_CLKSRC_LCD1, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS4210_CLKDIV_LCD1, .shift = 0, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_fimg2d",
+ },
+ .sources = &exynos4210_clkset_mout_g2d,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_IMAGE, .shift = 8, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_IMAGE, .shift = 0, .size = 4 },
+ },
+};
+
+static struct clk init_clocks_off[] = {
+ {
+ .name = "sataphy",
+ .id = -1,
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "sata",
+ .id = -1,
+ .parent = &exynos4_clk_aclk_133.clk,
+ .enable = exynos4_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "fimd",
+ .devname = "exynos4-fb.1",
+ .enable = exynos4_clk_ip_lcd1_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.9",
+ .enable = exynos4_clk_ip_image_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.11",
+ .enable = exynos4_clk_ip_lcd1_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "fimg2d",
+ .enable = exynos4_clk_ip_image_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4210_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+
+ return 0;
+}
+
+static void exynos4210_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos4210_clock_save, ARRAY_SIZE(exynos4210_clock_save));
+}
+
+#else
+#define exynos4210_clock_suspend NULL
+#define exynos4210_clock_resume NULL
+#endif
+
+static struct syscore_ops exynos4210_clock_syscore_ops = {
+ .suspend = exynos4210_clock_suspend,
+ .resume = exynos4210_clock_resume,
+};
+
+void __init exynos4210_register_clocks(void)
+{
+ int ptr;
+
+ exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_CPU;
+ exynos4_clk_mout_mpll.reg_src.shift = 8;
+ exynos4_clk_mout_mpll.reg_src.size = 1;
+
+ for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+ s3c_register_clksrc(sysclks[ptr], 1);
+
+ s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+ s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+ register_syscore_ops(&exynos4210_clock_syscore_ops);
+}
diff --git a/trunk/arch/arm/mach-exynos/clock-exynos4212.c b/trunk/arch/arm/mach-exynos/clock-exynos4212.c
new file mode 100644
index 000000000000..529476f8ec71
--- /dev/null
+++ b/trunk/arch/arm/mach-exynos/clock-exynos4212.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4212 - Clock support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+
+#include "common.h"
+#include "clock-exynos4.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos4212_clock_save[] = {
+ SAVE_ITEM(EXYNOS4_CLKSRC_IMAGE),
+ SAVE_ITEM(EXYNOS4_CLKDIV_IMAGE),
+ SAVE_ITEM(EXYNOS4212_CLKGATE_IP_IMAGE),
+ SAVE_ITEM(EXYNOS4212_CLKGATE_IP_PERIR),
+};
+#endif
+
+static int exynos4212_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP0, clk, enable);
+}
+
+static int exynos4212_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS4_CLKGATE_IP_ISP1, clk, enable);
+}
+
+static struct clk *clk_src_mpll_user_list[] = {
+ [0] = &clk_fin_mpll,
+ [1] = &exynos4_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources clk_src_mpll_user = {
+ .sources = clk_src_mpll_user_list,
+ .nr_sources = ARRAY_SIZE(clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk clk_mout_mpll_user = {
+ .clk = {
+ .name = "mout_mpll_user",
+ },
+ .sources = &clk_src_mpll_user,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_CPU, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos4x12_clk_mout_g2d0 = {
+ .clk = {
+ .name = "mout_g2d0",
+ },
+ .sources = &exynos4_clkset_mout_g2d0,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk exynos4x12_clk_mout_g2d1 = {
+ .clk = {
+ .name = "mout_g2d1",
+ },
+ .sources = &exynos4_clkset_mout_g2d1,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 24, .size = 1 },
+};
+
+static struct clk *exynos4x12_clkset_mout_g2d_list[] = {
+ [0] = &exynos4x12_clk_mout_g2d0.clk,
+ [1] = &exynos4x12_clk_mout_g2d1.clk,
+};
+
+static struct clksrc_sources exynos4x12_clkset_mout_g2d = {
+ .sources = exynos4x12_clkset_mout_g2d_list,
+ .nr_sources = ARRAY_SIZE(exynos4x12_clkset_mout_g2d_list),
+};
+
+static struct clksrc_clk *sysclks[] = {
+ &clk_mout_mpll_user,
+};
+
+static struct clksrc_clk clksrcs[] = {
+ {
+ .clk = {
+ .name = "sclk_fimg2d",
+ },
+ .sources = &exynos4x12_clkset_mout_g2d,
+ .reg_src = { .reg = EXYNOS4_CLKSRC_DMC, .shift = 28, .size = 1 },
+ .reg_div = { .reg = EXYNOS4_CLKDIV_DMC1, .shift = 0, .size = 4 },
+ },
+};
+
+static struct clk init_clocks_off[] = {
+ {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.9",
+ .enable = exynos4_clk_ip_dmc_ctrl,
+ .ctrlbit = (1 << 24),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.12",
+ .enable = exynos4212_clk_ip_isp0_ctrl,
+ .ctrlbit = (7 << 8),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.13",
+ .enable = exynos4212_clk_ip_isp1_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.14",
+ .enable = exynos4212_clk_ip_isp0_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.15",
+ .enable = exynos4212_clk_ip_isp0_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "flite",
+ .devname = "exynos-fimc-lite.0",
+ .enable = exynos4212_clk_ip_isp0_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "flite",
+ .devname = "exynos-fimc-lite.1",
+ .enable = exynos4212_clk_ip_isp0_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "fimg2d",
+ .enable = exynos4_clk_ip_dmc_ctrl,
+ .ctrlbit = (1 << 23),
+ },
+};
+
+#ifdef CONFIG_PM_SLEEP
+static int exynos4212_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+
+ return 0;
+}
+
+static void exynos4212_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos4212_clock_save, ARRAY_SIZE(exynos4212_clock_save));
+}
+
+#else
+#define exynos4212_clock_suspend NULL
+#define exynos4212_clock_resume NULL
+#endif
+
+static struct syscore_ops exynos4212_clock_syscore_ops = {
+ .suspend = exynos4212_clock_suspend,
+ .resume = exynos4212_clock_resume,
+};
+
+void __init exynos4212_register_clocks(void)
+{
+ int ptr;
+
+ /* usbphy1 is removed */
+ exynos4_clkset_group_list[4] = NULL;
+
+ /* mout_mpll_user is used */
+ exynos4_clkset_group_list[6] = &clk_mout_mpll_user.clk;
+ exynos4_clkset_aclk_top_list[0] = &clk_mout_mpll_user.clk;
+
+ exynos4_clk_mout_mpll.reg_src.reg = EXYNOS4_CLKSRC_DMC;
+ exynos4_clk_mout_mpll.reg_src.shift = 12;
+ exynos4_clk_mout_mpll.reg_src.size = 1;
+
+ for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
+ s3c_register_clksrc(sysclks[ptr], 1);
+
+ s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
+
+ s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+ s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
+
+ register_syscore_ops(&exynos4212_clock_syscore_ops);
+}
diff --git a/trunk/arch/arm/mach-exynos/clock-exynos5.c b/trunk/arch/arm/mach-exynos/clock-exynos5.c
new file mode 100644
index 000000000000..b0ea31fc9fb8
--- /dev/null
+++ b/trunk/arch/arm/mach-exynos/clock-exynos5.c
@@ -0,0 +1,1645 @@
+/*
+ * Copyright (c) 2012 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * Clock support for EXYNOS5 SoCs
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include
+#include
+#include
+#include
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "common.h"
+
+#ifdef CONFIG_PM_SLEEP
+static struct sleep_save exynos5_clock_save[] = {
+ SAVE_ITEM(EXYNOS5_CLKSRC_MASK_TOP),
+ SAVE_ITEM(EXYNOS5_CLKSRC_MASK_GSCL),
+ SAVE_ITEM(EXYNOS5_CLKSRC_MASK_DISP1_0),
+ SAVE_ITEM(EXYNOS5_CLKSRC_MASK_FSYS),
+ SAVE_ITEM(EXYNOS5_CLKSRC_MASK_MAUDIO),
+ SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC0),
+ SAVE_ITEM(EXYNOS5_CLKSRC_MASK_PERIC1),
+ SAVE_ITEM(EXYNOS5_CLKGATE_IP_GSCL),
+ SAVE_ITEM(EXYNOS5_CLKGATE_IP_DISP1),
+ SAVE_ITEM(EXYNOS5_CLKGATE_IP_MFC),
+ SAVE_ITEM(EXYNOS5_CLKGATE_IP_G3D),
+ SAVE_ITEM(EXYNOS5_CLKGATE_IP_GEN),
+ SAVE_ITEM(EXYNOS5_CLKGATE_IP_FSYS),
+ SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIC),
+ SAVE_ITEM(EXYNOS5_CLKGATE_IP_PERIS),
+ SAVE_ITEM(EXYNOS5_CLKGATE_BLOCK),
+ SAVE_ITEM(EXYNOS5_CLKDIV_TOP0),
+ SAVE_ITEM(EXYNOS5_CLKDIV_TOP1),
+ SAVE_ITEM(EXYNOS5_CLKDIV_GSCL),
+ SAVE_ITEM(EXYNOS5_CLKDIV_DISP1_0),
+ SAVE_ITEM(EXYNOS5_CLKDIV_GEN),
+ SAVE_ITEM(EXYNOS5_CLKDIV_MAUDIO),
+ SAVE_ITEM(EXYNOS5_CLKDIV_FSYS0),
+ SAVE_ITEM(EXYNOS5_CLKDIV_FSYS1),
+ SAVE_ITEM(EXYNOS5_CLKDIV_FSYS2),
+ SAVE_ITEM(EXYNOS5_CLKDIV_FSYS3),
+ SAVE_ITEM(EXYNOS5_CLKDIV_PERIC0),
+ SAVE_ITEM(EXYNOS5_CLKDIV_PERIC1),
+ SAVE_ITEM(EXYNOS5_CLKDIV_PERIC2),
+ SAVE_ITEM(EXYNOS5_CLKDIV_PERIC3),
+ SAVE_ITEM(EXYNOS5_CLKDIV_PERIC4),
+ SAVE_ITEM(EXYNOS5_CLKDIV_PERIC5),
+ SAVE_ITEM(EXYNOS5_SCLK_DIV_ISP),
+ SAVE_ITEM(EXYNOS5_CLKSRC_TOP0),
+ SAVE_ITEM(EXYNOS5_CLKSRC_TOP1),
+ SAVE_ITEM(EXYNOS5_CLKSRC_TOP2),
+ SAVE_ITEM(EXYNOS5_CLKSRC_TOP3),
+ SAVE_ITEM(EXYNOS5_CLKSRC_GSCL),
+ SAVE_ITEM(EXYNOS5_CLKSRC_DISP1_0),
+ SAVE_ITEM(EXYNOS5_CLKSRC_MAUDIO),
+ SAVE_ITEM(EXYNOS5_CLKSRC_FSYS),
+ SAVE_ITEM(EXYNOS5_CLKSRC_PERIC0),
+ SAVE_ITEM(EXYNOS5_CLKSRC_PERIC1),
+ SAVE_ITEM(EXYNOS5_SCLK_SRC_ISP),
+ SAVE_ITEM(EXYNOS5_EPLL_CON0),
+ SAVE_ITEM(EXYNOS5_EPLL_CON1),
+ SAVE_ITEM(EXYNOS5_EPLL_CON2),
+ SAVE_ITEM(EXYNOS5_VPLL_CON0),
+ SAVE_ITEM(EXYNOS5_VPLL_CON1),
+ SAVE_ITEM(EXYNOS5_VPLL_CON2),
+ SAVE_ITEM(EXYNOS5_PWR_CTRL1),
+ SAVE_ITEM(EXYNOS5_PWR_CTRL2),
+};
+#endif
+
+static struct clk exynos5_clk_sclk_dptxphy = {
+ .name = "sclk_dptx",
+};
+
+static struct clk exynos5_clk_sclk_hdmi24m = {
+ .name = "sclk_hdmi24m",
+ .rate = 24000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmi27m = {
+ .name = "sclk_hdmi27m",
+ .rate = 27000000,
+};
+
+static struct clk exynos5_clk_sclk_hdmiphy = {
+ .name = "sclk_hdmiphy",
+};
+
+static struct clk exynos5_clk_sclk_usbphy = {
+ .name = "sclk_usbphy",
+ .rate = 48000000,
+};
+
+static int exynos5_clksrc_mask_top_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_TOP, clk, enable);
+}
+
+static int exynos5_clksrc_mask_disp1_0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_DISP1_0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_FSYS, clk, enable);
+}
+
+static int exynos5_clksrc_mask_gscl_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_GSCL, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC0, clk, enable);
+}
+
+static int exynos5_clksrc_mask_peric1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKSRC_MASK_PERIC1, clk, enable);
+}
+
+static int exynos5_clk_ip_acp_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ACP, clk, enable);
+}
+
+static int exynos5_clk_ip_core_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_CORE, clk, enable);
+}
+
+static int exynos5_clk_ip_disp1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_DISP1, clk, enable);
+}
+
+static int exynos5_clk_ip_fsys_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_FSYS, clk, enable);
+}
+
+static int exynos5_clk_block_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_BLOCK, clk, enable);
+}
+
+static int exynos5_clk_ip_gen_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GEN, clk, enable);
+}
+
+static int exynos5_clk_ip_mfc_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_MFC, clk, enable);
+}
+
+static int exynos5_clk_ip_peric_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIC, clk, enable);
+}
+
+static int exynos5_clk_ip_peris_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_PERIS, clk, enable);
+}
+
+static int exynos5_clk_ip_gscl_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_GSCL, clk, enable);
+}
+
+static int exynos5_clk_ip_isp0_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP0, clk, enable);
+}
+
+static int exynos5_clk_ip_isp1_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(EXYNOS5_CLKGATE_IP_ISP1, clk, enable);
+}
+
+static int exynos5_clk_hdmiphy_ctrl(struct clk *clk, int enable)
+{
+ return s5p_gatectrl(S5P_HDMI_PHY_CONTROL, clk, enable);
+}
+
+/* Core list of CMU_CPU side */
+
+static struct clksrc_clk exynos5_clk_mout_apll = {
+ .clk = {
+ .name = "mout_apll",
+ },
+ .sources = &clk_src_apll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 0, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_apll = {
+ .clk = {
+ .name = "sclk_apll",
+ .parent = &exynos5_clk_mout_apll.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_fout = {
+ .clk = {
+ .name = "mout_bpll_fout",
+ },
+ .sources = &clk_src_bpll_fout,
+ .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_list[] = {
+ [0] = &clk_fin_bpll,
+ [1] = &exynos5_clk_mout_bpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll = {
+ .sources = exynos5_clk_src_bpll_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll = {
+ .clk = {
+ .name = "mout_bpll",
+ },
+ .sources = &exynos5_clk_src_bpll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_bpll_user_list[] = {
+ [0] = &clk_fin_mpll,
+ [1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_bpll_user = {
+ .sources = exynos5_clk_src_bpll_user_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clk_src_bpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_bpll_user = {
+ .clk = {
+ .name = "mout_bpll_user",
+ },
+ .sources = &exynos5_clk_src_bpll_user,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 24, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpll = {
+ .clk = {
+ .name = "mout_cpll",
+ },
+ .sources = &clk_src_cpll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 8, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_epll = {
+ .clk = {
+ .name = "mout_epll",
+ },
+ .sources = &clk_src_epll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 12, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_fout = {
+ .clk = {
+ .name = "mout_mpll_fout",
+ },
+ .sources = &clk_src_mpll_fout,
+ .reg_src = { .reg = EXYNOS5_PLL_DIV2_SEL, .shift = 4, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_mpll_list[] = {
+ [0] = &clk_fin_mpll,
+ [1] = &exynos5_clk_mout_mpll_fout.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll = {
+ .sources = exynos5_clk_src_mpll_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll = {
+ .clk = {
+ .name = "mout_mpll",
+ },
+ .sources = &exynos5_clk_src_mpll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_CORE1, .shift = 8, .size = 1 },
+};
+
+static struct clk *exynos_clkset_vpllsrc_list[] = {
+ [0] = &clk_fin_vpll,
+ [1] = &exynos5_clk_sclk_hdmi27m,
+};
+
+static struct clksrc_sources exynos5_clkset_vpllsrc = {
+ .sources = exynos_clkset_vpllsrc_list,
+ .nr_sources = ARRAY_SIZE(exynos_clkset_vpllsrc_list),
+};
+
+static struct clksrc_clk exynos5_clk_vpllsrc = {
+ .clk = {
+ .name = "vpll_src",
+ .enable = exynos5_clksrc_mask_top_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos5_clkset_vpllsrc,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 0, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_sclk_vpll_list[] = {
+ [0] = &exynos5_clk_vpllsrc.clk,
+ [1] = &clk_fout_vpll,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_vpll = {
+ .sources = exynos5_clkset_sclk_vpll_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_vpll_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_vpll = {
+ .clk = {
+ .name = "sclk_vpll",
+ },
+ .sources = &exynos5_clkset_sclk_vpll,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_pixel = {
+ .clk = {
+ .name = "sclk_pixel",
+ .parent = &exynos5_clk_sclk_vpll.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 28, .size = 4 },
+};
+
+static struct clk *exynos5_clkset_sclk_hdmi_list[] = {
+ [0] = &exynos5_clk_sclk_pixel.clk,
+ [1] = &exynos5_clk_sclk_hdmiphy,
+};
+
+static struct clksrc_sources exynos5_clkset_sclk_hdmi = {
+ .sources = exynos5_clkset_sclk_hdmi_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_sclk_hdmi_list),
+};
+
+static struct clksrc_clk exynos5_clk_sclk_hdmi = {
+ .clk = {
+ .name = "sclk_hdmi",
+ .enable = exynos5_clksrc_mask_disp1_0_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &exynos5_clkset_sclk_hdmi,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 20, .size = 1 },
+};
+
+static struct clksrc_clk *exynos5_sclk_tv[] = {
+ &exynos5_clk_sclk_pixel,
+ &exynos5_clk_sclk_hdmi,
+};
+
+static struct clk *exynos5_clk_src_mpll_user_list[] = {
+ [0] = &clk_fin_mpll,
+ [1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_mpll_user = {
+ .sources = exynos5_clk_src_mpll_user_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clk_src_mpll_user_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_mpll_user = {
+ .clk = {
+ .name = "mout_mpll_user",
+ },
+ .sources = &exynos5_clk_src_mpll_user,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP2, .shift = 20, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_mout_cpu_list[] = {
+ [0] = &exynos5_clk_mout_apll.clk,
+ [1] = &exynos5_clk_mout_mpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_mout_cpu = {
+ .sources = exynos5_clkset_mout_cpu_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_mout_cpu_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_cpu = {
+ .clk = {
+ .name = "mout_cpu",
+ },
+ .sources = &exynos5_clkset_mout_cpu,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_CPU, .shift = 16, .size = 1 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_armclk = {
+ .clk = {
+ .name = "dout_armclk",
+ .parent = &exynos5_clk_mout_cpu.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_arm2clk = {
+ .clk = {
+ .name = "dout_arm2clk",
+ .parent = &exynos5_clk_dout_armclk.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_CPU0, .shift = 28, .size = 3 },
+};
+
+static struct clk exynos5_clk_armclk = {
+ .name = "armclk",
+ .parent = &exynos5_clk_dout_arm2clk.clk,
+};
+
+/* Core list of CMU_CDREX side */
+
+static struct clk *exynos5_clkset_cdrex_list[] = {
+ [0] = &exynos5_clk_mout_mpll.clk,
+ [1] = &exynos5_clk_mout_bpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_cdrex = {
+ .sources = exynos5_clkset_cdrex_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_cdrex_list),
+};
+
+static struct clksrc_clk exynos5_clk_cdrex = {
+ .clk = {
+ .name = "clk_cdrex",
+ },
+ .sources = &exynos5_clkset_cdrex,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_CDREX, .shift = 4, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_CDREX, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_acp = {
+ .clk = {
+ .name = "aclk_acp",
+ .parent = &exynos5_clk_mout_mpll.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_pclk_acp = {
+ .clk = {
+ .name = "pclk_acp",
+ .parent = &exynos5_clk_aclk_acp.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_ACP, .shift = 4, .size = 3 },
+};
+
+/* Core list of CMU_TOP side */
+
+static struct clk *exynos5_clkset_aclk_top_list[] = {
+ [0] = &exynos5_clk_mout_mpll_user.clk,
+ [1] = &exynos5_clk_mout_bpll_user.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk = {
+ .sources = exynos5_clkset_aclk_top_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_top_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_400 = {
+ .clk = {
+ .name = "aclk_400",
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+};
+
+static struct clk *exynos5_clkset_aclk_333_166_list[] = {
+ [0] = &exynos5_clk_mout_cpll.clk,
+ [1] = &exynos5_clk_mout_mpll_user.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_333_166 = {
+ .sources = exynos5_clkset_aclk_333_166_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_333_166_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_333 = {
+ .clk = {
+ .name = "aclk_333",
+ },
+ .sources = &exynos5_clkset_aclk_333_166,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 16, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 20, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_166 = {
+ .clk = {
+ .name = "aclk_166",
+ },
+ .sources = &exynos5_clkset_aclk_333_166,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 8, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 8, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_266 = {
+ .clk = {
+ .name = "aclk_266",
+ .parent = &exynos5_clk_mout_mpll_user.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 16, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_200 = {
+ .clk = {
+ .name = "aclk_200",
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 12, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 12, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66_pre = {
+ .clk = {
+ .name = "aclk_66_pre",
+ .parent = &exynos5_clk_mout_mpll_user.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP1, .shift = 24, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_aclk_66 = {
+ .clk = {
+ .name = "aclk_66",
+ .parent = &exynos5_clk_aclk_66_pre.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 0, .size = 3 },
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid = {
+ .clk = {
+ .name = "mout_aclk_300_gscl_mid",
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 24, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_aclk_300_mid1_list[] = {
+ [0] = &exynos5_clk_sclk_vpll.clk,
+ [1] = &exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl_mid1 = {
+ .sources = exynos5_clkset_aclk_300_mid1_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_mid1_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl_mid1 = {
+ .clk = {
+ .name = "mout_aclk_300_gscl_mid1",
+ },
+ .sources = &exynos5_clkset_aclk_300_gscl_mid1,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP1, .shift = 12, .size = 1 },
+};
+
+static struct clk *exynos5_clkset_aclk_300_gscl_list[] = {
+ [0] = &exynos5_clk_mout_aclk_300_gscl_mid.clk,
+ [1] = &exynos5_clk_mout_aclk_300_gscl_mid1.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_aclk_300_gscl = {
+ .sources = exynos5_clkset_aclk_300_gscl_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_aclk_300_gscl_list),
+};
+
+static struct clksrc_clk exynos5_clk_mout_aclk_300_gscl = {
+ .clk = {
+ .name = "mout_aclk_300_gscl",
+ },
+ .sources = &exynos5_clkset_aclk_300_gscl,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 25, .size = 1 },
+};
+
+static struct clk *exynos5_clk_src_gscl_300_list[] = {
+ [0] = &clk_ext_xtal_mux,
+ [1] = &exynos5_clk_mout_aclk_300_gscl.clk,
+};
+
+static struct clksrc_sources exynos5_clk_src_gscl_300 = {
+ .sources = exynos5_clk_src_gscl_300_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clk_src_gscl_300_list),
+};
+
+static struct clksrc_clk exynos5_clk_aclk_300_gscl = {
+ .clk = {
+ .name = "aclk_300_gscl",
+ },
+ .sources = &exynos5_clk_src_gscl_300,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 10, .size = 1 },
+};
+
+static struct clk exynos5_init_clocks_off[] = {
+ {
+ .name = "timers",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 24),
+ }, {
+ .name = "tmu_apbif",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peris_ctrl,
+ .ctrlbit = (1 << 21),
+ }, {
+ .name = "rtc",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peris_ctrl,
+ .ctrlbit = (1 << 20),
+ }, {
+ .name = "watchdog",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peris_ctrl,
+ .ctrlbit = (1 << 19),
+ }, {
+ .name = "biu", /* bus interface unit clock */
+ .devname = "dw_mmc.0",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "biu",
+ .devname = "dw_mmc.1",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 13),
+ }, {
+ .name = "biu",
+ .devname = "dw_mmc.2",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 14),
+ }, {
+ .name = "biu",
+ .devname = "dw_mmc.3",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 15),
+ }, {
+ .name = "sata",
+ .devname = "exynos5-sata",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "sata-phy",
+ .devname = "exynos5-sata-phy",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 24),
+ }, {
+ .name = "i2c",
+ .devname = "exynos5-sata-phy-i2c",
+ .parent = &exynos5_clk_aclk_200.clk,
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 25),
+ }, {
+ .name = "mfc",
+ .devname = "s5p-mfc-v6",
+ .enable = exynos5_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "hdmi",
+ .devname = "exynos5-hdmi",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "hdmiphy",
+ .devname = "exynos5-hdmi",
+ .enable = exynos5_clk_hdmiphy_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "mixer",
+ .devname = "exynos5-mixer",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 5),
+ }, {
+ .name = "dp",
+ .devname = "exynos-dp",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "jpeg",
+ .enable = exynos5_clk_ip_gen_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "dsim0",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "iis",
+ .devname = "samsung-i2s.1",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 20),
+ }, {
+ .name = "iis",
+ .devname = "samsung-i2s.2",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 21),
+ }, {
+ .name = "pcm",
+ .devname = "samsung-pcm.1",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 22),
+ }, {
+ .name = "pcm",
+ .devname = "samsung-pcm.2",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 23),
+ }, {
+ .name = "spdif",
+ .devname = "samsung-spdif",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 26),
+ }, {
+ .name = "ac97",
+ .devname = "samsung-ac97",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 27),
+ }, {
+ .name = "usbhost",
+ .enable = exynos5_clk_ip_fsys_ctrl ,
+ .ctrlbit = (1 << 18),
+ }, {
+ .name = "usbotg",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "nfcon",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 22),
+ }, {
+ .name = "iop",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = ((1 << 30) | (1 << 26) | (1 << 23)),
+ }, {
+ .name = "core_iop",
+ .enable = exynos5_clk_ip_core_ctrl,
+ .ctrlbit = ((1 << 21) | (1 << 3)),
+ }, {
+ .name = "mcu_iop",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.0",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 6),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.1",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.2",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.3",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.4",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.5",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.6",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-i2c.7",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 13),
+ }, {
+ .name = "i2c",
+ .devname = "s3c2440-hdmiphy-i2c",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 14),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 16),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 17),
+ }, {
+ .name = "spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos5_clk_aclk_66.clk,
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 18),
+ }, {
+ .name = "gscl",
+ .devname = "exynos-gsc.0",
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "gscl",
+ .devname = "exynos-gsc.1",
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "gscl",
+ .devname = "exynos-gsc.2",
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "gscl",
+ .devname = "exynos-gsc.3",
+ .enable = exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.1",
+ .enable = &exynos5_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.0",
+ .enable = &exynos5_clk_ip_mfc_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.2",
+ .enable = &exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 9)
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.3",
+ .enable = &exynos5_clk_ip_gen_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.4",
+ .enable = &exynos5_clk_ip_gen_ctrl,
+ .ctrlbit = (1 << 6)
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.5",
+ .enable = &exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 7),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.6",
+ .enable = &exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 8),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.7",
+ .enable = &exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 9),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.8",
+ .enable = &exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 10),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.9",
+ .enable = &exynos5_clk_ip_isp0_ctrl,
+ .ctrlbit = (0x3F << 8),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.10",
+ .enable = &exynos5_clk_ip_isp1_ctrl,
+ .ctrlbit = (0xF << 4),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.11",
+ .enable = &exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 8)
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.12",
+ .enable = &exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 11),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.13",
+ .enable = &exynos5_clk_ip_gscl_ctrl,
+ .ctrlbit = (1 << 12),
+ }, {
+ .name = "sysmmu",
+ .devname = "exynos-sysmmu.14",
+ .enable = &exynos5_clk_ip_acp_ctrl,
+ .ctrlbit = (1 << 7)
+ }
+};
+
+static struct clk exynos5_init_clocks_on[] = {
+ {
+ .name = "uart",
+ .devname = "s5pv210-uart.0",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 0),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.1",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 1),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.2",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 2),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.3",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 3),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.4",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 4),
+ }, {
+ .name = "uart",
+ .devname = "s5pv210-uart.5",
+ .enable = exynos5_clk_ip_peric_ctrl,
+ .ctrlbit = (1 << 5),
+ }
+};
+
+static struct clk exynos5_clk_pdma0 = {
+ .name = "dma",
+ .devname = "dma-pl330.0",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 1),
+};
+
+static struct clk exynos5_clk_pdma1 = {
+ .name = "dma",
+ .devname = "dma-pl330.1",
+ .enable = exynos5_clk_ip_fsys_ctrl,
+ .ctrlbit = (1 << 2),
+};
+
+static struct clk exynos5_clk_mdma1 = {
+ .name = "dma",
+ .devname = "dma-pl330.2",
+ .enable = exynos5_clk_ip_gen_ctrl,
+ .ctrlbit = (1 << 4),
+};
+
+static struct clk exynos5_clk_fimd1 = {
+ .name = "fimd",
+ .devname = "exynos5-fb.1",
+ .enable = exynos5_clk_ip_disp1_ctrl,
+ .ctrlbit = (1 << 0),
+};
+
+static struct clk *exynos5_clkset_group_list[] = {
+ [0] = &clk_ext_xtal_mux,
+ [1] = NULL,
+ [2] = &exynos5_clk_sclk_hdmi24m,
+ [3] = &exynos5_clk_sclk_dptxphy,
+ [4] = &exynos5_clk_sclk_usbphy,
+ [5] = &exynos5_clk_sclk_hdmiphy,
+ [6] = &exynos5_clk_mout_mpll_user.clk,
+ [7] = &exynos5_clk_mout_epll.clk,
+ [8] = &exynos5_clk_sclk_vpll.clk,
+ [9] = &exynos5_clk_mout_cpll.clk,
+};
+
+static struct clksrc_sources exynos5_clkset_group = {
+ .sources = exynos5_clkset_group_list,
+ .nr_sources = ARRAY_SIZE(exynos5_clkset_group_list),
+};
+
+/* Possible clock sources for aclk_266_gscl_sub Mux */
+static struct clk *clk_src_gscl_266_list[] = {
+ [0] = &clk_ext_xtal_mux,
+ [1] = &exynos5_clk_aclk_266.clk,
+};
+
+static struct clksrc_sources clk_src_gscl_266 = {
+ .sources = clk_src_gscl_266_list,
+ .nr_sources = ARRAY_SIZE(clk_src_gscl_266_list),
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc0 = {
+ .clk = {
+ .name = "dout_mmc0",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc1 = {
+ .clk = {
+ .name = "dout_mmc1",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 4, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc2 = {
+ .clk = {
+ .name = "dout_mmc2",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 8, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc3 = {
+ .clk = {
+ .name = "dout_mmc3",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_dout_mmc4 = {
+ .clk = {
+ .name = "dout_mmc4",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS3, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart0 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.0",
+ .enable = exynos5_clksrc_mask_peric0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart1 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.1",
+ .enable = exynos5_clksrc_mask_peric0_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 4, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 4, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart2 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.2",
+ .enable = exynos5_clksrc_mask_peric0_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 8, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 8, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_uart3 = {
+ .clk = {
+ .name = "uclk1",
+ .devname = "exynos4210-uart.3",
+ .enable = exynos5_clksrc_mask_peric0_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC0, .shift = 12, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC0, .shift = 12, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
+ .clk = {
+ .name = "ciu", /* card interface unit clock */
+ .devname = "dw_mmc.0",
+ .parent = &exynos5_clk_dout_mmc0.clk,
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
+ .clk = {
+ .name = "ciu",
+ .devname = "dw_mmc.1",
+ .parent = &exynos5_clk_dout_mmc1.clk,
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 4),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
+ .clk = {
+ .name = "ciu",
+ .devname = "dw_mmc.2",
+ .parent = &exynos5_clk_dout_mmc2.clk,
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 8),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
+ .clk = {
+ .name = "ciu",
+ .devname = "dw_mmc.3",
+ .parent = &exynos5_clk_dout_mmc3.clk,
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 12),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS2, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi0 = {
+ .clk = {
+ .name = "mdout_spi",
+ .devname = "exynos4210-spi.0",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi1 = {
+ .clk = {
+ .name = "mdout_spi",
+ .devname = "exynos4210-spi.1",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 16, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_mdout_spi2 = {
+ .clk = {
+ .name = "mdout_spi",
+ .devname = "exynos4210-spi.2",
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_PERIC1, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi0 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.0",
+ .parent = &exynos5_clk_mdout_spi0.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi1 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.1",
+ .parent = &exynos5_clk_mdout_spi1.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC1, .shift = 24, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_spi2 = {
+ .clk = {
+ .name = "sclk_spi",
+ .devname = "exynos4210-spi.2",
+ .parent = &exynos5_clk_mdout_spi2.clk,
+ .enable = exynos5_clksrc_mask_peric1_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_PERIC2, .shift = 8, .size = 8 },
+};
+
+static struct clksrc_clk exynos5_clk_sclk_fimd1 = {
+ .clk = {
+ .name = "sclk_fimd",
+ .devname = "exynos5-fb.1",
+ .enable = exynos5_clksrc_mask_disp1_0_ctrl,
+ .ctrlbit = (1 << 0),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_DISP1_0, .shift = 0, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_DISP1_0, .shift = 0, .size = 4 },
+};
+
+static struct clksrc_clk exynos5_clksrcs[] = {
+ {
+ .clk = {
+ .name = "aclk_266_gscl",
+ },
+ .sources = &clk_src_gscl_266,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP3, .shift = 8, .size = 1 },
+ }, {
+ .clk = {
+ .name = "sclk_g3d",
+ .devname = "mali-t604.0",
+ .enable = exynos5_clk_block_ctrl,
+ .ctrlbit = (1 << 1),
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_TOP0, .shift = 20, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_TOP0, .shift = 24, .size = 3 },
+ }, {
+ .clk = {
+ .name = "sclk_sata",
+ .devname = "exynos5-sata",
+ .enable = exynos5_clksrc_mask_fsys_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &exynos5_clkset_aclk,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_FSYS, .shift = 24, .size = 1 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_FSYS0, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_gscl_wrap",
+ .devname = "s5p-mipi-csis.0",
+ .enable = exynos5_clksrc_mask_gscl_ctrl,
+ .ctrlbit = (1 << 24),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 24, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 24, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_gscl_wrap",
+ .devname = "s5p-mipi-csis.1",
+ .enable = exynos5_clksrc_mask_gscl_ctrl,
+ .ctrlbit = (1 << 28),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 28, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 28, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam0",
+ .enable = exynos5_clksrc_mask_gscl_ctrl,
+ .ctrlbit = (1 << 16),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 16, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 16, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_cam1",
+ .enable = exynos5_clksrc_mask_gscl_ctrl,
+ .ctrlbit = (1 << 20),
+ },
+ .sources = &exynos5_clkset_group,
+ .reg_src = { .reg = EXYNOS5_CLKSRC_GSCL, .shift = 20, .size = 4 },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GSCL, .shift = 20, .size = 4 },
+ }, {
+ .clk = {
+ .name = "sclk_jpeg",
+ .parent = &exynos5_clk_mout_cpll.clk,
+ },
+ .reg_div = { .reg = EXYNOS5_CLKDIV_GEN, .shift = 4, .size = 3 },
+ },
+};
+
+/* Clock initialization code */
+static struct clksrc_clk *exynos5_sysclks[] = {
+ &exynos5_clk_mout_apll,
+ &exynos5_clk_sclk_apll,
+ &exynos5_clk_mout_bpll,
+ &exynos5_clk_mout_bpll_fout,
+ &exynos5_clk_mout_bpll_user,
+ &exynos5_clk_mout_cpll,
+ &exynos5_clk_mout_epll,
+ &exynos5_clk_mout_mpll,
+ &exynos5_clk_mout_mpll_fout,
+ &exynos5_clk_mout_mpll_user,
+ &exynos5_clk_vpllsrc,
+ &exynos5_clk_sclk_vpll,
+ &exynos5_clk_mout_cpu,
+ &exynos5_clk_dout_armclk,
+ &exynos5_clk_dout_arm2clk,
+ &exynos5_clk_cdrex,
+ &exynos5_clk_aclk_400,
+ &exynos5_clk_aclk_333,
+ &exynos5_clk_aclk_266,
+ &exynos5_clk_aclk_200,
+ &exynos5_clk_aclk_166,
+ &exynos5_clk_aclk_300_gscl,
+ &exynos5_clk_mout_aclk_300_gscl,
+ &exynos5_clk_mout_aclk_300_gscl_mid,
+ &exynos5_clk_mout_aclk_300_gscl_mid1,
+ &exynos5_clk_aclk_66_pre,
+ &exynos5_clk_aclk_66,
+ &exynos5_clk_dout_mmc0,
+ &exynos5_clk_dout_mmc1,
+ &exynos5_clk_dout_mmc2,
+ &exynos5_clk_dout_mmc3,
+ &exynos5_clk_dout_mmc4,
+ &exynos5_clk_aclk_acp,
+ &exynos5_clk_pclk_acp,
+ &exynos5_clk_sclk_spi0,
+ &exynos5_clk_sclk_spi1,
+ &exynos5_clk_sclk_spi2,
+ &exynos5_clk_mdout_spi0,
+ &exynos5_clk_mdout_spi1,
+ &exynos5_clk_mdout_spi2,
+ &exynos5_clk_sclk_fimd1,
+};
+
+static struct clk *exynos5_clk_cdev[] = {
+ &exynos5_clk_pdma0,
+ &exynos5_clk_pdma1,
+ &exynos5_clk_mdma1,
+ &exynos5_clk_fimd1,
+};
+
+static struct clksrc_clk *exynos5_clksrc_cdev[] = {
+ &exynos5_clk_sclk_uart0,
+ &exynos5_clk_sclk_uart1,
+ &exynos5_clk_sclk_uart2,
+ &exynos5_clk_sclk_uart3,
+ &exynos5_clk_sclk_mmc0,
+ &exynos5_clk_sclk_mmc1,
+ &exynos5_clk_sclk_mmc2,
+ &exynos5_clk_sclk_mmc3,
+};
+
+static struct clk_lookup exynos5_clk_lookup[] = {
+ CLKDEV_INIT("exynos4210-uart.0", "clk_uart_baud0", &exynos5_clk_sclk_uart0.clk),
+ CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
+ CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
+ CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
+ CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
+ CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
+ CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
+ CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
+ CLKDEV_INIT("exynos4210-spi.0", "spi_busclk0", &exynos5_clk_sclk_spi0.clk),
+ CLKDEV_INIT("exynos4210-spi.1", "spi_busclk0", &exynos5_clk_sclk_spi1.clk),
+ CLKDEV_INIT("exynos4210-spi.2", "spi_busclk0", &exynos5_clk_sclk_spi2.clk),
+ CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
+ CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
+ CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
+ CLKDEV_INIT("exynos5-fb.1", "lcd", &exynos5_clk_fimd1),
+};
+
+static unsigned long exynos5_epll_get_rate(struct clk *clk)
+{
+ return clk->rate;
+}
+
+static struct clk *exynos5_clks[] __initdata = {
+ &exynos5_clk_sclk_hdmi27m,
+ &exynos5_clk_sclk_hdmiphy,
+ &clk_fout_bpll,
+ &clk_fout_bpll_div2,
+ &clk_fout_cpll,
+ &clk_fout_mpll_div2,
+ &exynos5_clk_armclk,
+};
+
+static u32 epll_div[][6] = {
+ { 192000000, 0, 48, 3, 1, 0 },
+ { 180000000, 0, 45, 3, 1, 0 },
+ { 73728000, 1, 73, 3, 3, 47710 },
+ { 67737600, 1, 90, 4, 3, 20762 },
+ { 49152000, 0, 49, 3, 3, 9961 },
+ { 45158400, 0, 45, 3, 3, 10381 },
+ { 180633600, 0, 45, 3, 1, 10381 },
+};
+
+static int exynos5_epll_set_rate(struct clk *clk, unsigned long rate)
+{
+ unsigned int epll_con, epll_con_k;
+ unsigned int i;
+ unsigned int tmp;
+ unsigned int epll_rate;
+ unsigned int locktime;
+ unsigned int lockcnt;
+
+ /* Return if nothing changed */
+ if (clk->rate == rate)
+ return 0;
+
+ if (clk->parent)
+ epll_rate = clk_get_rate(clk->parent);
+ else
+ epll_rate = clk_ext_xtal_mux.rate;
+
+ if (epll_rate != 24000000) {
+ pr_err("Invalid Clock : recommended clock is 24MHz.\n");
+ return -EINVAL;
+ }
+
+ epll_con = __raw_readl(EXYNOS5_EPLL_CON0);
+ epll_con &= ~(0x1 << 27 | \
+ PLL46XX_MDIV_MASK << PLL46XX_MDIV_SHIFT | \
+ PLL46XX_PDIV_MASK << PLL46XX_PDIV_SHIFT | \
+ PLL46XX_SDIV_MASK << PLL46XX_SDIV_SHIFT);
+
+ for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
+ if (epll_div[i][0] == rate) {
+ epll_con_k = epll_div[i][5] << 0;
+ epll_con |= epll_div[i][1] << 27;
+ epll_con |= epll_div[i][2] << PLL46XX_MDIV_SHIFT;
+ epll_con |= epll_div[i][3] << PLL46XX_PDIV_SHIFT;
+ epll_con |= epll_div[i][4] << PLL46XX_SDIV_SHIFT;
+ break;
+ }
+ }
+
+ if (i == ARRAY_SIZE(epll_div)) {
+ printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ epll_rate /= 1000000;
+
+ /* 3000 max_cycls : specification data */
+ locktime = 3000 / epll_rate * epll_div[i][3];
+ lockcnt = locktime * 10000 / (10000 / epll_rate);
+
+ __raw_writel(lockcnt, EXYNOS5_EPLL_LOCK);
+
+ __raw_writel(epll_con, EXYNOS5_EPLL_CON0);
+ __raw_writel(epll_con_k, EXYNOS5_EPLL_CON1);
+
+ do {
+ tmp = __raw_readl(EXYNOS5_EPLL_CON0);
+ } while (!(tmp & 0x1 << EXYNOS5_EPLLCON0_LOCKED_SHIFT));
+
+ clk->rate = rate;
+
+ return 0;
+}
+
+static struct clk_ops exynos5_epll_ops = {
+ .get_rate = exynos5_epll_get_rate,
+ .set_rate = exynos5_epll_set_rate,
+};
+
+static int xtal_rate;
+
+static unsigned long exynos5_fout_apll_get_rate(struct clk *clk)
+{
+ return s5p_get_pll35xx(xtal_rate, __raw_readl(EXYNOS5_APLL_CON0));
+}
+
+static struct clk_ops exynos5_fout_apll_ops = {
+ .get_rate = exynos5_fout_apll_get_rate,
+};
+
+#ifdef CONFIG_PM
+static int exynos5_clock_suspend(void)
+{
+ s3c_pm_do_save(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+
+ return 0;
+}
+
+static void exynos5_clock_resume(void)
+{
+ s3c_pm_do_restore_core(exynos5_clock_save, ARRAY_SIZE(exynos5_clock_save));
+}
+#else
+#define exynos5_clock_suspend NULL
+#define exynos5_clock_resume NULL
+#endif
+
+static struct syscore_ops exynos5_clock_syscore_ops = {
+ .suspend = exynos5_clock_suspend,
+ .resume = exynos5_clock_resume,
+};
+
+void __init_or_cpufreq exynos5_setup_clocks(void)
+{
+ struct clk *xtal_clk;
+ unsigned long apll;
+ unsigned long bpll;
+ unsigned long cpll;
+ unsigned long mpll;
+ unsigned long epll;
+ unsigned long vpll;
+ unsigned long vpllsrc;
+ unsigned long xtal;
+ unsigned long armclk;
+ unsigned long mout_cdrex;
+ unsigned long aclk_400;
+ unsigned long aclk_333;
+ unsigned long aclk_266;
+ unsigned long aclk_200;
+ unsigned long aclk_166;
+ unsigned long aclk_66;
+ unsigned int ptr;
+
+ printk(KERN_DEBUG "%s: registering clocks\n", __func__);
+
+ xtal_clk = clk_get(NULL, "xtal");
+ BUG_ON(IS_ERR(xtal_clk));
+
+ xtal = clk_get_rate(xtal_clk);
+
+ xtal_rate = xtal;
+
+ clk_put(xtal_clk);
+
+ printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
+
+ apll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_APLL_CON0));
+ bpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_BPLL_CON0));
+ cpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_CPLL_CON0));
+ mpll = s5p_get_pll35xx(xtal, __raw_readl(EXYNOS5_MPLL_CON0));
+ epll = s5p_get_pll36xx(xtal, __raw_readl(EXYNOS5_EPLL_CON0),
+ __raw_readl(EXYNOS5_EPLL_CON1));
+
+ vpllsrc = clk_get_rate(&exynos5_clk_vpllsrc.clk);
+ vpll = s5p_get_pll36xx(vpllsrc, __raw_readl(EXYNOS5_VPLL_CON0),
+ __raw_readl(EXYNOS5_VPLL_CON1));
+
+ clk_fout_apll.ops = &exynos5_fout_apll_ops;
+ clk_fout_bpll.rate = bpll;
+ clk_fout_bpll_div2.rate = bpll >> 1;
+ clk_fout_cpll.rate = cpll;
+ clk_fout_mpll.rate = mpll;
+ clk_fout_mpll_div2.rate = mpll >> 1;
+ clk_fout_epll.rate = epll;
+ clk_fout_vpll.rate = vpll;
+
+ printk(KERN_INFO "EXYNOS5: PLL settings, A=%ld, B=%ld, C=%ld\n"
+ "M=%ld, E=%ld V=%ld",
+ apll, bpll, cpll, mpll, epll, vpll);
+
+ armclk = clk_get_rate(&exynos5_clk_armclk);
+ mout_cdrex = clk_get_rate(&exynos5_clk_cdrex.clk);
+
+ aclk_400 = clk_get_rate(&exynos5_clk_aclk_400.clk);
+ aclk_333 = clk_get_rate(&exynos5_clk_aclk_333.clk);
+ aclk_266 = clk_get_rate(&exynos5_clk_aclk_266.clk);
+ aclk_200 = clk_get_rate(&exynos5_clk_aclk_200.clk);
+ aclk_166 = clk_get_rate(&exynos5_clk_aclk_166.clk);
+ aclk_66 = clk_get_rate(&exynos5_clk_aclk_66.clk);
+
+ printk(KERN_INFO "EXYNOS5: ARMCLK=%ld, CDREX=%ld, ACLK400=%ld\n"
+ "ACLK333=%ld, ACLK266=%ld, ACLK200=%ld\n"
+ "ACLK166=%ld, ACLK66=%ld\n",
+ armclk, mout_cdrex, aclk_400,
+ aclk_333, aclk_266, aclk_200,
+ aclk_166, aclk_66);
+
+
+ clk_fout_epll.ops = &exynos5_epll_ops;
+
+ if (clk_set_parent(&exynos5_clk_mout_epll.clk, &clk_fout_epll))
+ printk(KERN_ERR "Unable to set parent %s of clock %s.\n",
+ clk_fout_epll.name, exynos5_clk_mout_epll.clk.name);
+
+ clk_set_rate(&exynos5_clk_sclk_apll.clk, 100000000);
+ clk_set_rate(&exynos5_clk_aclk_266.clk, 300000000);
+
+ clk_set_rate(&exynos5_clk_aclk_acp.clk, 267000000);
+ clk_set_rate(&exynos5_clk_pclk_acp.clk, 134000000);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrcs); ptr++)
+ s3c_set_clksrc(&exynos5_clksrcs[ptr], true);
+}
+
+void __init exynos5_register_clocks(void)
+{
+ int ptr;
+
+ s3c24xx_register_clocks(exynos5_clks, ARRAY_SIZE(exynos5_clks));
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sysclks); ptr++)
+ s3c_register_clksrc(exynos5_sysclks[ptr], 1);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos5_sclk_tv); ptr++)
+ s3c_register_clksrc(exynos5_sclk_tv[ptr], 1);
+
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clksrc_cdev); ptr++)
+ s3c_register_clksrc(exynos5_clksrc_cdev[ptr], 1);
+
+ s3c_register_clksrc(exynos5_clksrcs, ARRAY_SIZE(exynos5_clksrcs));
+ s3c_register_clocks(exynos5_init_clocks_on, ARRAY_SIZE(exynos5_init_clocks_on));
+
+ s3c24xx_register_clocks(exynos5_clk_cdev, ARRAY_SIZE(exynos5_clk_cdev));
+ for (ptr = 0; ptr < ARRAY_SIZE(exynos5_clk_cdev); ptr++)
+ s3c_disable_clocks(exynos5_clk_cdev[ptr], 1);
+
+ s3c_register_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+ s3c_disable_clocks(exynos5_init_clocks_off, ARRAY_SIZE(exynos5_init_clocks_off));
+ clkdev_add_table(exynos5_clk_lookup, ARRAY_SIZE(exynos5_clk_lookup));
+
+ register_syscore_ops(&exynos5_clock_syscore_ops);
+ s3c_pwmclk_init();
+}
diff --git a/trunk/arch/arm/mach-exynos/common.c b/trunk/arch/arm/mach-exynos/common.c
index 46089fe24705..15718da30c45 100644
--- a/trunk/arch/arm/mach-exynos/common.c
+++ b/trunk/arch/arm/mach-exynos/common.c
@@ -24,8 +24,6 @@
#include
#include
#include
-#include
-#include
#include
#include
@@ -39,9 +37,9 @@
#include
#include
#include
-#include
#include
+#include
#include
#include
#include
@@ -67,16 +65,17 @@ static const char name_exynos5440[] = "EXYNOS5440";
static void exynos4_map_io(void);
static void exynos5_map_io(void);
static void exynos5440_map_io(void);
+static void exynos4_init_clocks(int xtal);
+static void exynos5_init_clocks(int xtal);
static void exynos4_init_uarts(struct s3c2410_uartcfg *cfg, int no);
static int exynos_init(void);
-unsigned long xxti_f = 0, xusbxti_f = 0;
-
static struct cpu_table cpu_ids[] __initdata = {
{
.idcode = EXYNOS4210_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
+ .init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4210,
@@ -84,6 +83,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = EXYNOS4212_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
+ .init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4212,
@@ -91,6 +91,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = EXYNOS4412_CPU_ID,
.idmask = EXYNOS4_CPU_MASK,
.map_io = exynos4_map_io,
+ .init_clocks = exynos4_init_clocks,
.init_uarts = exynos4_init_uarts,
.init = exynos_init,
.name = name_exynos4412,
@@ -98,6 +99,7 @@ static struct cpu_table cpu_ids[] __initdata = {
.idcode = EXYNOS5250_SOC_ID,
.idmask = EXYNOS5_SOC_MASK,
.map_io = exynos5_map_io,
+ .init_clocks = exynos5_init_clocks,
.init = exynos_init,
.name = name_exynos5250,
}, {
@@ -233,33 +235,6 @@ static struct map_desc exynos4_iodesc1[] __initdata = {
},
};
-static struct map_desc exynos4210_iodesc[] __initdata = {
- {
- .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
- .pfn = __phys_to_pfn(EXYNOS4210_PA_SYSRAM_NS),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-};
-
-static struct map_desc exynos4x12_iodesc[] __initdata = {
- {
- .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
- .pfn = __phys_to_pfn(EXYNOS4x12_PA_SYSRAM_NS),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-};
-
-static struct map_desc exynos5250_iodesc[] __initdata = {
- {
- .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
- .pfn = __phys_to_pfn(EXYNOS5250_PA_SYSRAM_NS),
- .length = SZ_4K,
- .type = MT_DEVICE,
- },
-};
-
static struct map_desc exynos5_iodesc[] __initdata = {
{
.virtual = (unsigned long)S3C_VA_SYS,
@@ -281,6 +256,11 @@ static struct map_desc exynos5_iodesc[] __initdata = {
.pfn = __phys_to_pfn(EXYNOS5_PA_SROMC),
.length = SZ_4K,
.type = MT_DEVICE,
+ }, {
+ .virtual = (unsigned long)S5P_VA_SYSTIMER,
+ .pfn = __phys_to_pfn(EXYNOS5_PA_SYSTIMER),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
}, {
.virtual = (unsigned long)S5P_VA_SYSRAM,
.pfn = __phys_to_pfn(EXYNOS5_PA_SYSRAM),
@@ -388,11 +368,6 @@ static void __init exynos4_map_io(void)
else
iotable_init(exynos4_iodesc1, ARRAY_SIZE(exynos4_iodesc1));
- if (soc_is_exynos4210())
- iotable_init(exynos4210_iodesc, ARRAY_SIZE(exynos4210_iodesc));
- if (soc_is_exynos4212() || soc_is_exynos4412())
- iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
-
/* initialize device information early */
exynos4_default_sdhci0();
exynos4_default_sdhci1();
@@ -425,9 +400,22 @@ static void __init exynos4_map_io(void)
static void __init exynos5_map_io(void)
{
iotable_init(exynos5_iodesc, ARRAY_SIZE(exynos5_iodesc));
+}
- if (soc_is_exynos5250())
- iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
+static void __init exynos4_init_clocks(int xtal)
+{
+ printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+ s3c24xx_register_baseclocks(xtal);
+ s5p_register_clocks(xtal);
+
+ if (soc_is_exynos4210())
+ exynos4210_register_clocks();
+ else if (soc_is_exynos4212() || soc_is_exynos4412())
+ exynos4212_register_clocks();
+
+ exynos4_register_clocks();
+ exynos4_setup_clocks();
}
static void __init exynos5440_map_io(void)
@@ -435,21 +423,22 @@ static void __init exynos5440_map_io(void)
iotable_init(exynos5440_iodesc0, ARRAY_SIZE(exynos5440_iodesc0));
}
-void __init exynos_init_time(void)
+static void __init exynos5_init_clocks(int xtal)
{
- if (of_have_populated_dt()) {
-#ifdef CONFIG_OF
- of_clk_init(NULL);
- clocksource_of_init();
-#endif
- } else {
- /* todo: remove after migrating legacy E4 platforms to dt */
-#ifdef CONFIG_ARCH_EXYNOS4
- exynos4_clk_init(NULL);
- exynos4_clk_register_fixed_ext(xxti_f, xusbxti_f);
+ printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
+
+ /* EXYNOS5440 can support only common clock framework */
+
+ if (soc_is_exynos5440())
+ return;
+
+#ifdef CONFIG_SOC_EXYNOS5250
+ s3c24xx_register_baseclocks(xtal);
+ s5p_register_clocks(xtal);
+
+ exynos5_register_clocks();
+ exynos5_setup_clocks();
#endif
- mct_init();
- }
}
void __init exynos4_init_irq(void)
@@ -835,7 +824,6 @@ static int __init exynos_init_irq_eint(void)
static const struct of_device_id exynos_pinctrl_ids[] = {
{ .compatible = "samsung,exynos4210-pinctrl", },
{ .compatible = "samsung,exynos4x12-pinctrl", },
- { .compatible = "samsung,exynos5250-pinctrl", },
};
struct device_node *pctrl_np, *wkup_np;
const char *wkup_compat = "samsung,exynos4210-wakeup-eint";
@@ -889,30 +877,3 @@ static int __init exynos_init_irq_eint(void)
return 0;
}
arch_initcall(exynos_init_irq_eint);
-
-static struct resource exynos4_pmu_resource[] = {
- DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU),
- DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU1),
-#if defined(CONFIG_SOC_EXYNOS4412)
- DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU2),
- DEFINE_RES_IRQ(EXYNOS4_IRQ_PMU_CPU3),
-#endif
-};
-
-static struct platform_device exynos4_device_pmu = {
- .name = "arm-pmu",
- .num_resources = ARRAY_SIZE(exynos4_pmu_resource),
- .resource = exynos4_pmu_resource,
-};
-
-static int __init exynos_armpmu_init(void)
-{
- if (!of_have_populated_dt()) {
- if (soc_is_exynos4210() || soc_is_exynos4212())
- exynos4_device_pmu.num_resources = 2;
- platform_device_register(&exynos4_device_pmu);
- }
-
- return 0;
-}
-arch_initcall(exynos_armpmu_init);
diff --git a/trunk/arch/arm/mach-exynos/common.h b/trunk/arch/arm/mach-exynos/common.h
index b17448c1a164..9339bb8954be 100644
--- a/trunk/arch/arm/mach-exynos/common.h
+++ b/trunk/arch/arm/mach-exynos/common.h
@@ -12,11 +12,7 @@
#ifndef __ARCH_ARM_MACH_EXYNOS_COMMON_H
#define __ARCH_ARM_MACH_EXYNOS_COMMON_H
-#include
-
-extern void mct_init(void);
-void exynos_init_time(void);
-extern unsigned long xxti_f, xusbxti_f;
+extern void exynos4_timer_init(void);
struct map_desc;
void exynos_init_io(struct map_desc *mach_desc, int size);
@@ -26,12 +22,6 @@ void exynos4_restart(char mode, const char *cmd);
void exynos5_restart(char mode, const char *cmd);
void exynos_init_late(void);
-/* ToDo: remove these after migrating legacy exynos4 platforms to dt */
-void exynos4_clk_init(struct device_node *np);
-void exynos4_clk_register_fixed_ext(unsigned long, unsigned long);
-
-void exynos_firmware_init(void);
-
#ifdef CONFIG_PM_GENERIC_DOMAINS
int exynos_pm_late_initcall(void);
#else
diff --git a/trunk/arch/arm/mach-exynos/exynos-smc.S b/trunk/arch/arm/mach-exynos/exynos-smc.S
deleted file mode 100644
index 2e27aa3813fd..000000000000
--- a/trunk/arch/arm/mach-exynos/exynos-smc.S
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics.
- *
- * Copied from omap-smc.S Copyright (C) 2010 Texas Instruments, Inc.
- *
- * This program is free software,you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include
-
-/*
- * Function signature: void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3)
- */
-
-ENTRY(exynos_smc)
- stmfd sp!, {r4-r11, lr}
- dsb
- smc #0
- ldmfd sp!, {r4-r11, pc}
-ENDPROC(exynos_smc)
diff --git a/trunk/arch/arm/mach-exynos/firmware.c b/trunk/arch/arm/mach-exynos/firmware.c
deleted file mode 100644
index ed11f100d479..000000000000
--- a/trunk/arch/arm/mach-exynos/firmware.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * Copyright (C) 2012 Samsung Electronics.
- * Kyungmin Park
- * Tomasz Figa
- *
- * This program is free software,you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include
-#include
-#include
-#include
-#include
-
-#include
-
-#include
-
-#include "smc.h"
-
-static int exynos_do_idle(void)
-{
- exynos_smc(SMC_CMD_SLEEP, 0, 0, 0);
- return 0;
-}
-
-static int exynos_cpu_boot(int cpu)
-{
- exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0);
- return 0;
-}
-
-static int exynos_set_cpu_boot_addr(int cpu, unsigned long boot_addr)
-{
- void __iomem *boot_reg = S5P_VA_SYSRAM_NS + 0x1c + 4*cpu;
-
- __raw_writel(boot_addr, boot_reg);
- return 0;
-}
-
-static const struct firmware_ops exynos_firmware_ops = {
- .do_idle = exynos_do_idle,
- .set_cpu_boot_addr = exynos_set_cpu_boot_addr,
- .cpu_boot = exynos_cpu_boot,
-};
-
-void __init exynos_firmware_init(void)
-{
- if (of_have_populated_dt()) {
- struct device_node *nd;
- const __be32 *addr;
-
- nd = of_find_compatible_node(NULL, NULL,
- "samsung,secure-firmware");
- if (!nd)
- return;
-
- addr = of_get_address(nd, 0, NULL, NULL);
- if (!addr) {
- pr_err("%s: No address specified.\n", __func__);
- return;
- }
- }
-
- pr_info("Running under secure firmware.\n");
-
- register_firmware_ops(&exynos_firmware_ops);
-}
diff --git a/trunk/arch/arm/mach-exynos/hotplug.c b/trunk/arch/arm/mach-exynos/hotplug.c
index af90cfa2f826..c3f825b27947 100644
--- a/trunk/arch/arm/mach-exynos/hotplug.c
+++ b/trunk/arch/arm/mach-exynos/hotplug.c
@@ -28,6 +28,7 @@ static inline void cpu_enter_lowpower_a9(void)
{
unsigned int v;
+ flush_cache_all();
asm volatile(
" mcr p15, 0, %1, c7, c5, 0\n"
" mcr p15, 0, %1, c7, c10, 4\n"
diff --git a/trunk/arch/arm/mach-exynos/include/mach/irqs.h b/trunk/arch/arm/mach-exynos/include/mach/irqs.h
index c72f59d91fce..8bd5dde5fc78 100644
--- a/trunk/arch/arm/mach-exynos/include/mach/irqs.h
+++ b/trunk/arch/arm/mach-exynos/include/mach/irqs.h
@@ -30,6 +30,8 @@
/* For EXYNOS4 and EXYNOS5 */
+#define EXYNOS_IRQ_MCT_LOCALTIMER IRQ_PPI(12)
+
#define EXYNOS_IRQ_EINT16_31 IRQ_SPI(32)
/* For EXYNOS4 SoCs */
@@ -126,7 +128,7 @@
#define EXYNOS4_IRQ_ADC1 IRQ_SPI(107)
#define EXYNOS4_IRQ_PEN1 IRQ_SPI(108)
#define EXYNOS4_IRQ_KEYPAD IRQ_SPI(109)
-#define EXYNOS4_IRQ_POWER_PMU IRQ_SPI(110)
+#define EXYNOS4_IRQ_PMU IRQ_SPI(110)
#define EXYNOS4_IRQ_GPS IRQ_SPI(111)
#define EXYNOS4_IRQ_INTFEEDCTRL_SSS IRQ_SPI(112)
#define EXYNOS4_IRQ_SLIMBUS IRQ_SPI(113)
@@ -134,11 +136,6 @@
#define EXYNOS4_IRQ_TSI IRQ_SPI(115)
#define EXYNOS4_IRQ_SATA IRQ_SPI(116)
-#define EXYNOS4_IRQ_PMU COMBINER_IRQ(2, 2)
-#define EXYNOS4_IRQ_PMU_CPU1 COMBINER_IRQ(3, 2)
-#define EXYNOS4_IRQ_PMU_CPU2 COMBINER_IRQ(18, 2)
-#define EXYNOS4_IRQ_PMU_CPU3 COMBINER_IRQ(19, 2)
-
#define EXYNOS4_IRQ_TMU_TRIG0 COMBINER_IRQ(2, 4)
#define EXYNOS4_IRQ_TMU_TRIG1 COMBINER_IRQ(3, 4)
@@ -171,10 +168,7 @@
#define EXYNOS4_IRQ_FIMD0_VSYNC COMBINER_IRQ(11, 1)
#define EXYNOS4_IRQ_FIMD0_SYSTEM COMBINER_IRQ(11, 2)
-#define EXYNOS4210_MAX_COMBINER_NR 16
-#define EXYNOS4212_MAX_COMBINER_NR 18
-#define EXYNOS4412_MAX_COMBINER_NR 20
-#define EXYNOS4_MAX_COMBINER_NR EXYNOS4412_MAX_COMBINER_NR
+#define EXYNOS4_MAX_COMBINER_NR 16
#define EXYNOS4_IRQ_GPIO1_NR_GROUPS 16
#define EXYNOS4_IRQ_GPIO2_NR_GROUPS 9
@@ -239,6 +233,7 @@
#define IRQ_TC EXYNOS4_IRQ_PEN0
#define IRQ_KEYPAD EXYNOS4_IRQ_KEYPAD
+#define IRQ_PMU EXYNOS4_IRQ_PMU
#define IRQ_FIMD0_FIFO EXYNOS4_IRQ_FIMD0_FIFO
#define IRQ_FIMD0_VSYNC EXYNOS4_IRQ_FIMD0_VSYNC
@@ -328,6 +323,8 @@
#define EXYNOS5_IRQ_CEC IRQ_SPI(114)
#define EXYNOS5_IRQ_SATA IRQ_SPI(115)
+#define EXYNOS5_IRQ_MCT_L0 IRQ_SPI(120)
+#define EXYNOS5_IRQ_MCT_L1 IRQ_SPI(121)
#define EXYNOS5_IRQ_MMC44 IRQ_SPI(123)
#define EXYNOS5_IRQ_MDMA1 IRQ_SPI(124)
#define EXYNOS5_IRQ_FIMC_LITE0 IRQ_SPI(125)
@@ -422,6 +419,8 @@
#define EXYNOS5_IRQ_PMU_CPU1 COMBINER_IRQ(22, 4)
#define EXYNOS5_IRQ_EINT0 COMBINER_IRQ(23, 0)
+#define EXYNOS5_IRQ_MCT_G0 COMBINER_IRQ(23, 3)
+#define EXYNOS5_IRQ_MCT_G1 COMBINER_IRQ(23, 4)
#define EXYNOS5_IRQ_EINT1 COMBINER_IRQ(24, 0)
#define EXYNOS5_IRQ_SYSMMU_LITE1_0 COMBINER_IRQ(24, 1)
diff --git a/trunk/arch/arm/mach-exynos/include/mach/map.h b/trunk/arch/arm/mach-exynos/include/mach/map.h
index 99e0a79f3b1f..1df6abbf53b8 100644
--- a/trunk/arch/arm/mach-exynos/include/mach/map.h
+++ b/trunk/arch/arm/mach-exynos/include/mach/map.h
@@ -26,9 +26,6 @@
#define EXYNOS4_PA_SYSRAM0 0x02025000
#define EXYNOS4_PA_SYSRAM1 0x02020000
#define EXYNOS5_PA_SYSRAM 0x02020000
-#define EXYNOS4210_PA_SYSRAM_NS 0x0203F000
-#define EXYNOS4x12_PA_SYSRAM_NS 0x0204F000
-#define EXYNOS5250_PA_SYSRAM_NS 0x0204F000
#define EXYNOS4_PA_FIMC0 0x11800000
#define EXYNOS4_PA_FIMC1 0x11810000
@@ -68,6 +65,7 @@
#define EXYNOS5_PA_CMU 0x10010000
#define EXYNOS4_PA_SYSTIMER 0x10050000
+#define EXYNOS5_PA_SYSTIMER 0x101C0000
#define EXYNOS4_PA_WATCHDOG 0x10060000
#define EXYNOS5_PA_WATCHDOG 0x101D0000
diff --git a/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h b/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h
new file mode 100644
index 000000000000..80dd02ad6d61
--- /dev/null
+++ b/trunk/arch/arm/mach-exynos/include/mach/regs-mct.h
@@ -0,0 +1,53 @@
+/* arch/arm/mach-exynos4/include/mach/regs-mct.h
+ *
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
+ * EXYNOS4 MCT configutation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_REGS_MCT_H
+#define __ASM_ARCH_REGS_MCT_H __FILE__
+
+#include
+
+#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
+
+#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
+#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
+#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
+
+#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
+#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
+#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
+
+#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
+
+#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
+#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
+#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
+
+#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
+#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
+#define EXYNOS4_MCT_L_MASK (0xffffff00)
+
+#define MCT_L_TCNTB_OFFSET (0x00)
+#define MCT_L_ICNTB_OFFSET (0x08)
+#define MCT_L_TCON_OFFSET (0x20)
+#define MCT_L_INT_CSTAT_OFFSET (0x30)
+#define MCT_L_INT_ENB_OFFSET (0x34)
+#define MCT_L_WSTAT_OFFSET (0x40)
+
+#define MCT_G_TCON_START (1 << 8)
+#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
+#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
+
+#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
+#define MCT_L_TCON_INT_START (1 << 1)
+#define MCT_L_TCON_TIMER_START (1 << 0)
+
+#endif /* __ASM_ARCH_REGS_MCT_H */
diff --git a/trunk/arch/arm/mach-exynos/mach-armlex4210.c b/trunk/arch/arm/mach-exynos/mach-armlex4210.c
index 5f0f55701374..2126f3503a3f 100644
--- a/trunk/arch/arm/mach-exynos/mach-armlex4210.c
+++ b/trunk/arch/arm/mach-exynos/mach-armlex4210.c
@@ -178,6 +178,7 @@ static void __init armlex4210_smsc911x_init(void)
static void __init armlex4210_map_io(void)
{
exynos_init_io(NULL, 0);
+ s3c24xx_init_clocks(24000000);
s3c24xx_init_uarts(armlex4210_uartcfgs,
ARRAY_SIZE(armlex4210_uartcfgs));
}
@@ -202,6 +203,6 @@ MACHINE_START(ARMLEX4210, "ARMLEX4210")
.map_io = armlex4210_map_io,
.init_machine = armlex4210_machine_init,
.init_late = exynos_init_late,
- .init_time = exynos_init_time,
+ .init_time = exynos4_timer_init,
.restart = exynos4_restart,
MACHINE_END
diff --git a/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c b/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c
index b9ed834a7eee..3358088c822a 100644
--- a/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c
+++ b/trunk/arch/arm/mach-exynos/mach-exynos4-dt.c
@@ -11,26 +11,121 @@
* published by the Free Software Foundation.
*/
-#include
#include
-#include
#include
-#include
-#include
#include
-#include
+#include
+
+#include
+#include
#include "common.h"
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the Exynos4 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART0,
+ "exynos4210-uart.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART1,
+ "exynos4210-uart.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART2,
+ "exynos4210-uart.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS4_PA_UART3,
+ "exynos4210-uart.3", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(0),
+ "exynos4-sdhci.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(1),
+ "exynos4-sdhci.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(2),
+ "exynos4-sdhci.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-sdhci", EXYNOS4_PA_HSMMC(3),
+ "exynos4-sdhci.3", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(0),
+ "s3c2440-i2c.0", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(1),
+ "s3c2440-i2c.1", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(2),
+ "s3c2440-i2c.2", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(3),
+ "s3c2440-i2c.3", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(4),
+ "s3c2440-i2c.4", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(5),
+ "s3c2440-i2c.5", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(6),
+ "s3c2440-i2c.6", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS4_PA_IIC(7),
+ "s3c2440-i2c.7", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI0,
+ "exynos4210-spi.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI1,
+ "exynos4210-spi.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS4_PA_SPI2,
+ "exynos4210-spi.2", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA0, "dma-pl330.0", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_PDMA1, "dma-pl330.1", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
+ "exynos-tmu", NULL),
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
+ "exynos-sysmmu.0", NULL), /* MFC_L */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
+ "exynos-sysmmu.1", NULL), /* MFC_R */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
+ "exynos-sysmmu.2", NULL), /* TV */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
+ "exynos-sysmmu.3", NULL), /* JPEG */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
+ "exynos-sysmmu.4", NULL), /* ROTATOR */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
+ "exynos-sysmmu.5", NULL), /* FIMC0 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
+ "exynos-sysmmu.6", NULL), /* FIMC1 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
+ "exynos-sysmmu.7", NULL), /* FIMC2 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
+ "exynos-sysmmu.8", NULL), /* FIMC3 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
+ "exynos-sysmmu.9", NULL), /* G2D(4210) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
+ "exynos-sysmmu.9", NULL), /* G2D(4x12) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
+ "exynos-sysmmu.10", NULL), /* FIMD0 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
+ "exynos-sysmmu.11", NULL), /* FIMD1(4210) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
+ "exynos-sysmmu.12", NULL), /* IS0(4x12) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
+ "exynos-sysmmu.13", NULL), /* IS1(4x12) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
+ "exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
+ "exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
+ {},
+};
+
static void __init exynos4_dt_map_io(void)
{
exynos_init_io(NULL, 0);
+ s3c24xx_init_clocks(24000000);
}
static void __init exynos4_dt_machine_init(void)
{
- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ of_platform_populate(NULL, of_default_bus_match_table,
+ exynos4_auxdata_lookup, NULL);
}
static char const *exynos4_dt_compat[] __initdata = {
@@ -40,28 +135,14 @@ static char const *exynos4_dt_compat[] __initdata = {
NULL
};
-static void __init exynos4_reserve(void)
-{
-#ifdef CONFIG_S5P_DEV_MFC
- struct s5p_mfc_dt_meminfo mfc_mem;
-
- /* Reserve memory for MFC only if it's available */
- mfc_mem.compatible = "samsung,mfc-v5";
- if (of_scan_flat_dt(s5p_fdt_find_mfc_mem, &mfc_mem))
- s5p_mfc_reserve_mem(mfc_mem.roff, mfc_mem.rsize, mfc_mem.loff,
- mfc_mem.lsize);
-#endif
-}
DT_MACHINE_START(EXYNOS4210_DT, "Samsung Exynos4 (Flattened Device Tree)")
/* Maintainer: Thomas Abraham */
.smp = smp_ops(exynos_smp_ops),
.init_irq = exynos4_init_irq,
.map_io = exynos4_dt_map_io,
- .init_early = exynos_firmware_init,
.init_machine = exynos4_dt_machine_init,
.init_late = exynos_init_late,
- .init_time = exynos_init_time,
+ .init_time = exynos4_timer_init,
.dt_compat = exynos4_dt_compat,
.restart = exynos4_restart,
- .reserve = exynos4_reserve,
MACHINE_END
diff --git a/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c b/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c
index 753b94f3fca7..acaeb14db54b 100644
--- a/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/trunk/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,21 +11,151 @@
#include
#include
+#include
#include
#include
-#include
#include
+#include
#include
#include
+#include
#include
#include "common.h"
+/*
+ * The following lookup table is used to override device names when devices
+ * are registered from device tree. This is temporarily added to enable
+ * device tree support addition for the EXYNOS5 architecture.
+ *
+ * For drivers that require platform data to be provided from the machine
+ * file, a platform data pointer can also be supplied along with the
+ * devices names. Usually, the platform data elements that cannot be parsed
+ * from the device tree by the drivers (example: function pointers) are
+ * supplied. But it should be noted that this is a temporary mechanism and
+ * at some point, the drivers should be capable of parsing all the platform
+ * data from the device tree.
+ */
+static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART0,
+ "exynos4210-uart.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART1,
+ "exynos4210-uart.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART2,
+ "exynos4210-uart.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5_PA_UART3,
+ "exynos4210-uart.3", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(0),
+ "s3c2440-i2c.0", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(1),
+ "s3c2440-i2c.1", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(2),
+ "s3c2440-i2c.2", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(3),
+ "s3c2440-i2c.3", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(4),
+ "s3c2440-i2c.4", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(5),
+ "s3c2440-i2c.5", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(6),
+ "s3c2440-i2c.6", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-i2c", EXYNOS5_PA_IIC(7),
+ "s3c2440-i2c.7", NULL),
+ OF_DEV_AUXDATA("samsung,s3c2440-hdmiphy-i2c", EXYNOS5_PA_IIC(8),
+ "s3c2440-hdmiphy-i2c", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI0,
+ "dw_mmc.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI1,
+ "dw_mmc.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI2,
+ "dw_mmc.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5250-dw-mshc", EXYNOS5_PA_DWMCI3,
+ "dw_mmc.3", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI0,
+ "exynos4210-spi.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI1,
+ "exynos4210-spi.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos4210-spi", EXYNOS5_PA_SPI2,
+ "exynos4210-spi.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-sata-ahci", 0x122F0000,
+ "exynos5-sata", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-sata-phy", 0x12170000,
+ "exynos5-sata-phy", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-sata-phy-i2c", 0x121D0000,
+ "exynos5-sata-phy-i2c", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA0, "dma-pl330.0", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_PDMA1, "dma-pl330.1", NULL),
+ OF_DEV_AUXDATA("arm,pl330", EXYNOS5_PA_MDMA1, "dma-pl330.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC0,
+ "exynos-gsc.0", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC1,
+ "exynos-gsc.1", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC2,
+ "exynos-gsc.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
+ "exynos-gsc.3", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-hdmi", 0x14530000,
+ "exynos5-hdmi", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5-mixer", 0x14450000,
+ "exynos5-mixer", NULL),
+ OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
+ OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
+ "exynos-tmu", NULL),
+ OF_DEV_AUXDATA("samsung,i2s-v5", 0x03830000,
+ "samsung-i2s.0", NULL),
+ OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D60000,
+ "samsung-i2s.1", NULL),
+ OF_DEV_AUXDATA("samsung,i2s-v5", 0x12D70000,
+ "samsung-i2s.2", NULL),
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
+ "exynos-sysmmu.0", "mfc"), /* MFC_L */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
+ "exynos-sysmmu.1", "mfc"), /* MFC_R */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
+ "exynos-sysmmu.2", NULL), /* TV */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
+ "exynos-sysmmu.3", "jpeg"), /* JPEG */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
+ "exynos-sysmmu.4", NULL), /* ROTATOR */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
+ "exynos-sysmmu.5", "gscl"), /* GSCL0 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
+ "exynos-sysmmu.6", "gscl"), /* GSCL1 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
+ "exynos-sysmmu.7", "gscl"), /* GSCL2 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
+ "exynos-sysmmu.8", "gscl"), /* GSCL3 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
+ "exynos-sysmmu.9", NULL), /* FIMC-IS0 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
+ "exynos-sysmmu.10", NULL), /* FIMC-IS1 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
+ "exynos-sysmmu.11", NULL), /* FIMD1 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
+ "exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
+ "exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
+ OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
+ "exynos-sysmmu.14", NULL), /* G2D */
+ {},
+};
+
+static const struct of_dev_auxdata exynos5440_auxdata_lookup[] __initconst = {
+ OF_DEV_AUXDATA("samsung,exynos4210-uart", EXYNOS5440_PA_UART0,
+ "exynos4210-uart.0", NULL),
+ {},
+};
+
static void __init exynos5_dt_map_io(void)
{
+ unsigned long root = of_get_flat_dt_root();
+
exynos_init_io(NULL, 0);
+
+ if (of_flat_dt_is_compatible(root, "samsung,exynos5250"))
+ s3c24xx_init_clocks(24000000);
}
static void __init exynos5_dt_machine_init(void)
@@ -52,7 +182,12 @@ static void __init exynos5_dt_machine_init(void)
}
}
- of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ if (of_machine_is_compatible("samsung,exynos5250"))
+ of_platform_populate(NULL, of_default_bus_match_table,
+ exynos5250_auxdata_lookup, NULL);
+ else if (of_machine_is_compatible("samsung,exynos5440"))
+ of_platform_populate(NULL, of_default_bus_match_table,
+ exynos5440_auxdata_lookup, NULL);
}
static char const *exynos5_dt_compat[] __initdata = {
@@ -81,7 +216,7 @@ DT_MACHINE_START(EXYNOS5_DT, "SAMSUNG EXYNOS5 (Flattened Device Tree)")
.map_io = exynos5_dt_map_io,
.init_machine = exynos5_dt_machine_init,
.init_late = exynos_init_late,
- .init_time = exynos_init_time,
+ .init_time = exynos4_timer_init,
.dt_compat = exynos5_dt_compat,
.restart = exynos5_restart,
.reserve = exynos5_reserve,
diff --git a/trunk/arch/arm/mach-exynos/mach-nuri.c b/trunk/arch/arm/mach-exynos/mach-nuri.c
index 5c8b2878dbbd..ab920e34bd0a 100644
--- a/trunk/arch/arm/mach-exynos/mach-nuri.c
+++ b/trunk/arch/arm/mach-exynos/mach-nuri.c
@@ -1252,7 +1252,7 @@ static void __init nuri_camera_init(void)
}
m5mols_board_info.irq = s5p_register_gpio_interrupt(GPIO_CAM_8M_ISP_INT);
- if (m5mols_board_info.irq >= 0)
+ if (!IS_ERR_VALUE(m5mols_board_info.irq))
s3c_gpio_cfgpin(GPIO_CAM_8M_ISP_INT, S3C_GPIO_SFN(0xF));
else
pr_err("%s: Failed to configure 8M_ISP_INT GPIO\n", __func__);
@@ -1331,9 +1331,8 @@ static struct platform_device *nuri_devices[] __initdata = {
static void __init nuri_map_io(void)
{
exynos_init_io(NULL, 0);
+ s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
- xxti_f = 0;
- xusbxti_f = 24000000;
}
static void __init nuri_reserve(void)
@@ -1382,7 +1381,7 @@ MACHINE_START(NURI, "NURI")
.map_io = nuri_map_io,
.init_machine = nuri_machine_init,
.init_late = exynos_init_late,
- .init_time = exynos_init_time,
+ .init_time = exynos4_timer_init,
.reserve = &nuri_reserve,
.restart = exynos4_restart,
MACHINE_END
diff --git a/trunk/arch/arm/mach-exynos/mach-origen.c b/trunk/arch/arm/mach-exynos/mach-origen.c
index 27f03ed5d067..ec42024dd13f 100644
--- a/trunk/arch/arm/mach-exynos/mach-origen.c
+++ b/trunk/arch/arm/mach-exynos/mach-origen.c
@@ -755,9 +755,8 @@ static void s5p_tv_setup(void)
static void __init origen_map_io(void)
{
exynos_init_io(NULL, 0);
+ s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs));
- xxti_f = 0;
- xusbxti_f = 24000000;
}
static void __init origen_power_init(void)
@@ -817,7 +816,7 @@ MACHINE_START(ORIGEN, "ORIGEN")
.map_io = origen_map_io,
.init_machine = origen_machine_init,
.init_late = exynos_init_late,
- .init_time = exynos_init_time,
+ .init_time = exynos4_timer_init,
.reserve = &origen_reserve,
.restart = exynos4_restart,
MACHINE_END
diff --git a/trunk/arch/arm/mach-exynos/mach-smdk4x12.c b/trunk/arch/arm/mach-exynos/mach-smdk4x12.c
index 2c8af9617920..5df91236dbb4 100644
--- a/trunk/arch/arm/mach-exynos/mach-smdk4x12.c
+++ b/trunk/arch/arm/mach-exynos/mach-smdk4x12.c
@@ -323,6 +323,7 @@ static struct platform_device *smdk4x12_devices[] __initdata = {
static void __init smdk4x12_map_io(void)
{
exynos_init_io(NULL, 0);
+ s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(smdk4x12_uartcfgs, ARRAY_SIZE(smdk4x12_uartcfgs));
}
@@ -376,7 +377,7 @@ MACHINE_START(SMDK4212, "SMDK4212")
.init_irq = exynos4_init_irq,
.map_io = smdk4x12_map_io,
.init_machine = smdk4x12_machine_init,
- .init_time = exynos_init_time,
+ .init_time = exynos4_timer_init,
.restart = exynos4_restart,
.reserve = &smdk4x12_reserve,
MACHINE_END
@@ -390,7 +391,7 @@ MACHINE_START(SMDK4412, "SMDK4412")
.map_io = smdk4x12_map_io,
.init_machine = smdk4x12_machine_init,
.init_late = exynos_init_late,
- .init_time = exynos_init_time,
+ .init_time = exynos4_timer_init,
.restart = exynos4_restart,
.reserve = &smdk4x12_reserve,
MACHINE_END
diff --git a/trunk/arch/arm/mach-exynos/mach-smdkv310.c b/trunk/arch/arm/mach-exynos/mach-smdkv310.c
index d95b8cf85253..9680e1291065 100644
--- a/trunk/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/trunk/arch/arm/mach-exynos/mach-smdkv310.c
@@ -372,9 +372,8 @@ static void s5p_tv_setup(void)
static void __init smdkv310_map_io(void)
{
exynos_init_io(NULL, 0);
+ s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(smdkv310_uartcfgs, ARRAY_SIZE(smdkv310_uartcfgs));
- xxti_f = 12000000;
- xusbxti_f = 24000000;
}
static void __init smdkv310_reserve(void)
@@ -425,7 +424,7 @@ MACHINE_START(SMDKV310, "SMDKV310")
.init_irq = exynos4_init_irq,
.map_io = smdkv310_map_io,
.init_machine = smdkv310_machine_init,
- .init_time = exynos_init_time,
+ .init_time = exynos4_timer_init,
.reserve = &smdkv310_reserve,
.restart = exynos4_restart,
MACHINE_END
@@ -438,7 +437,7 @@ MACHINE_START(SMDKC210, "SMDKC210")
.map_io = smdkv310_map_io,
.init_machine = smdkv310_machine_init,
.init_late = exynos_init_late,
- .init_time = exynos_init_time,
+ .init_time = exynos4_timer_init,
.reserve = &smdkv310_reserve,
.restart = exynos4_restart,
MACHINE_END
diff --git a/trunk/arch/arm/mach-exynos/mach-universal_c210.c b/trunk/arch/arm/mach-exynos/mach-universal_c210.c
index 327d50d4681d..d28c7fbaba2d 100644
--- a/trunk/arch/arm/mach-exynos/mach-universal_c210.c
+++ b/trunk/arch/arm/mach-exynos/mach-universal_c210.c
@@ -41,7 +41,7 @@
#include
#include
#include
-#include
+#include
#include
#include
@@ -1093,10 +1093,9 @@ static struct platform_device *universal_devices[] __initdata = {
static void __init universal_map_io(void)
{
exynos_init_io(NULL, 0);
+ s3c24xx_init_clocks(clk_xusbxti.rate);
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
- samsung_set_timer_source(SAMSUNG_PWM2, SAMSUNG_PWM4);
- xxti_f = 0;
- xusbxti_f = 24000000;
+ s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
}
static void s5p_tv_setup(void)
@@ -1154,7 +1153,7 @@ MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
.map_io = universal_map_io,
.init_machine = universal_machine_init,
.init_late = exynos_init_late,
- .init_time = samsung_timer_init,
+ .init_time = s5p_timer_init,
.reserve = &universal_reserve,
.restart = exynos4_restart,
MACHINE_END
diff --git a/trunk/drivers/clocksource/exynos_mct.c b/trunk/arch/arm/mach-exynos/mct.c
similarity index 64%
rename from trunk/drivers/clocksource/exynos_mct.c
rename to trunk/arch/arm/mach-exynos/mct.c
index 661026834b23..c9d6650f9b5d 100644
--- a/trunk/drivers/clocksource/exynos_mct.c
+++ b/trunk/arch/arm/mach-exynos/mct.c
@@ -20,9 +20,6 @@
#include
#include
#include
-#include
-#include
-#include
#include
#include
@@ -31,36 +28,9 @@
#include
#include
+#include
#include
-#define EXYNOS4_MCTREG(x) (x)
-#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
-#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
-#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
-#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
-#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
-#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
-#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
-#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
-#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
-#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
-#define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300)
-#define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x))
-#define EXYNOS4_MCT_L_MASK (0xffffff00)
-
-#define MCT_L_TCNTB_OFFSET (0x00)
-#define MCT_L_ICNTB_OFFSET (0x08)
-#define MCT_L_TCON_OFFSET (0x20)
-#define MCT_L_INT_CSTAT_OFFSET (0x30)
-#define MCT_L_INT_ENB_OFFSET (0x34)
-#define MCT_L_WSTAT_OFFSET (0x40)
-#define MCT_G_TCON_START (1 << 8)
-#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
-#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
-#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
-#define MCT_L_TCON_INT_START (1 << 1)
-#define MCT_L_TCON_TIMER_START (1 << 0)
-
#define TICK_BASE_CNT 1
enum {
@@ -68,75 +38,64 @@ enum {
MCT_INT_PPI
};
-enum {
- MCT_G0_IRQ,
- MCT_G1_IRQ,
- MCT_G2_IRQ,
- MCT_G3_IRQ,
- MCT_L0_IRQ,
- MCT_L1_IRQ,
- MCT_L2_IRQ,
- MCT_L3_IRQ,
- MCT_NR_IRQS,
-};
-
-static void __iomem *reg_base;
static unsigned long clk_rate;
static unsigned int mct_int_type;
-static int mct_irqs[MCT_NR_IRQS];
struct mct_clock_event_device {
struct clock_event_device *evt;
- unsigned long base;
+ void __iomem *base;
char name[10];
};
-static void exynos4_mct_write(unsigned int value, unsigned long offset)
+static void exynos4_mct_write(unsigned int value, void *addr)
{
- unsigned long stat_addr;
+ void __iomem *stat_addr;
u32 mask;
u32 i;
- __raw_writel(value, reg_base + offset);
+ __raw_writel(value, addr);
- if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) {
- stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET;
- switch (offset & EXYNOS4_MCT_L_MASK) {
- case MCT_L_TCON_OFFSET:
+ if (likely(addr >= EXYNOS4_MCT_L_BASE(0))) {
+ u32 base = (u32) addr & EXYNOS4_MCT_L_MASK;
+ switch ((u32) addr & ~EXYNOS4_MCT_L_MASK) {
+ case (u32) MCT_L_TCON_OFFSET:
+ stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
mask = 1 << 3; /* L_TCON write status */
break;
- case MCT_L_ICNTB_OFFSET:
+ case (u32) MCT_L_ICNTB_OFFSET:
+ stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
mask = 1 << 1; /* L_ICNTB write status */
break;
- case MCT_L_TCNTB_OFFSET:
+ case (u32) MCT_L_TCNTB_OFFSET:
+ stat_addr = (void __iomem *) base + MCT_L_WSTAT_OFFSET;
mask = 1 << 0; /* L_TCNTB write status */
break;
default:
return;
}
} else {
- switch (offset) {
- case EXYNOS4_MCT_G_TCON:
+ switch ((u32) addr) {
+ case (u32) EXYNOS4_MCT_G_TCON:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 16; /* G_TCON write status */
break;
- case EXYNOS4_MCT_G_COMP0_L:
+ case (u32) EXYNOS4_MCT_G_COMP0_L:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 0; /* G_COMP0_L write status */
break;
- case EXYNOS4_MCT_G_COMP0_U:
+ case (u32) EXYNOS4_MCT_G_COMP0_U:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 1; /* G_COMP0_U write status */
break;
- case EXYNOS4_MCT_G_COMP0_ADD_INCR:
+ case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
stat_addr = EXYNOS4_MCT_G_WSTAT;
mask = 1 << 2; /* G_COMP0_ADD_INCR w status */
break;
- case EXYNOS4_MCT_G_CNT_L:
+ case (u32) EXYNOS4_MCT_G_CNT_L:
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
mask = 1 << 0; /* G_CNT_L write status */
break;
- case EXYNOS4_MCT_G_CNT_U:
+ case (u32) EXYNOS4_MCT_G_CNT_U:
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
mask = 1 << 1; /* G_CNT_U write status */
break;
@@ -147,12 +106,12 @@ static void exynos4_mct_write(unsigned int value, unsigned long offset)
/* Wait maximum 1 ms until written values are applied */
for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
- if (__raw_readl(reg_base + stat_addr) & mask) {
- __raw_writel(mask, reg_base + stat_addr);
+ if (__raw_readl(stat_addr) & mask) {
+ __raw_writel(mask, stat_addr);
return;
}
- panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset);
+ panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
}
/* Clocksource handling */
@@ -163,7 +122,7 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
- reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ reg = __raw_readl(EXYNOS4_MCT_G_TCON);
reg |= MCT_G_TCON_START;
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
}
@@ -171,12 +130,12 @@ static void exynos4_mct_frc_start(u32 hi, u32 lo)
static cycle_t exynos4_frc_read(struct clocksource *cs)
{
unsigned int lo, hi;
- u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
+ u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
do {
hi = hi2;
- lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L);
- hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U);
+ lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
+ hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
} while (hi != hi2);
return ((cycle_t)hi << 32) | lo;
@@ -208,7 +167,7 @@ static void exynos4_mct_comp0_stop(void)
{
unsigned int tcon;
- tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
@@ -221,7 +180,7 @@ static void exynos4_mct_comp0_start(enum clock_event_mode mode,
unsigned int tcon;
cycle_t comp_cycle;
- tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON);
+ tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
if (mode == CLOCK_EVT_MODE_PERIODIC) {
tcon |= MCT_G_TCON_COMP0_AUTO_INC;
@@ -298,7 +257,11 @@ static void exynos4_clockevent_init(void)
mct_comp_device.cpumask = cpumask_of(0);
clockevents_config_and_register(&mct_comp_device, clk_rate,
0xf, 0xffffffff);
- setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
+
+ if (soc_is_exynos5250())
+ setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
+ else
+ setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
}
#ifdef CONFIG_LOCAL_TIMERS
@@ -310,12 +273,12 @@ static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
{
unsigned long tmp;
unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
- unsigned long offset = mevt->base + MCT_L_TCON_OFFSET;
+ void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
- tmp = __raw_readl(reg_base + offset);
+ tmp = __raw_readl(addr);
if (tmp & mask) {
tmp &= ~mask;
- exynos4_mct_write(tmp, offset);
+ exynos4_mct_write(tmp, addr);
}
}
@@ -334,7 +297,7 @@ static void exynos4_mct_tick_start(unsigned long cycles,
/* enable MCT tick interrupt */
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
- tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET);
+ tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
MCT_L_TCON_INTERVAL_MODE;
exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
@@ -386,7 +349,7 @@ static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt)
exynos4_mct_tick_stop(mevt);
/* Clear the MCT tick interrupt */
- if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
+ if (__raw_readl(mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) {
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
return 1;
} else {
@@ -422,6 +385,7 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
{
struct mct_clock_event_device *mevt;
unsigned int cpu = smp_processor_id();
+ int mct_lx_irq;
mevt = this_cpu_ptr(&percpu_mct_tick);
mevt->evt = evt;
@@ -442,17 +406,21 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
if (mct_int_type == MCT_INT_SPI) {
if (cpu == 0) {
+ mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
+ EXYNOS5_IRQ_MCT_L0;
mct_tick0_event_irq.dev_id = mevt;
- evt->irq = mct_irqs[MCT_L0_IRQ];
- setup_irq(evt->irq, &mct_tick0_event_irq);
+ evt->irq = mct_lx_irq;
+ setup_irq(mct_lx_irq, &mct_tick0_event_irq);
} else {
+ mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
+ EXYNOS5_IRQ_MCT_L1;
mct_tick1_event_irq.dev_id = mevt;
- evt->irq = mct_irqs[MCT_L1_IRQ];
- setup_irq(evt->irq, &mct_tick1_event_irq);
- irq_set_affinity(evt->irq, cpumask_of(1));
+ evt->irq = mct_lx_irq;
+ setup_irq(mct_lx_irq, &mct_tick1_event_irq);
+ irq_set_affinity(mct_lx_irq, cpumask_of(1));
}
} else {
- enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
+ enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0);
}
return 0;
@@ -468,7 +436,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt)
else
remove_irq(evt->irq, &mct_tick1_event_irq);
else
- disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
+ disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER);
}
static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
@@ -477,92 +445,41 @@ static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
};
#endif /* CONFIG_LOCAL_TIMERS */
-static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base)
+static void __init exynos4_timer_resources(void)
{
- struct clk *mct_clk, *tick_clk;
-
- tick_clk = np ? of_clk_get_by_name(np, "fin_pll") :
- clk_get(NULL, "fin_pll");
- if (IS_ERR(tick_clk))
- panic("%s: unable to determine tick clock rate\n", __func__);
- clk_rate = clk_get_rate(tick_clk);
+ struct clk *mct_clk;
+ mct_clk = clk_get(NULL, "xtal");
- mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct");
- if (IS_ERR(mct_clk))
- panic("%s: unable to retrieve mct clock instance\n", __func__);
- clk_prepare_enable(mct_clk);
-
- reg_base = base;
- if (!reg_base)
- panic("%s: unable to ioremap mct address space\n", __func__);
+ clk_rate = clk_get_rate(mct_clk);
#ifdef CONFIG_LOCAL_TIMERS
if (mct_int_type == MCT_INT_PPI) {
int err;
- err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
+ err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER,
exynos4_mct_tick_isr, "MCT",
&percpu_mct_tick);
WARN(err, "MCT: can't request IRQ %d (%d)\n",
- mct_irqs[MCT_L0_IRQ], err);
+ EXYNOS_IRQ_MCT_LOCALTIMER, err);
}
local_timer_register(&exynos4_mct_tick_ops);
#endif /* CONFIG_LOCAL_TIMERS */
}
-void __init mct_init(void)
+void __init exynos4_timer_init(void)
{
- if (soc_is_exynos4210()) {
- mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
- mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
- mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
- mct_int_type = MCT_INT_SPI;
- } else {
- panic("unable to determine mct controller type\n");
+ if (soc_is_exynos5440()) {
+ arch_timer_of_register();
+ return;
}
- exynos4_timer_resources(NULL, S5P_VA_SYSTIMER);
- exynos4_clocksource_init();
- exynos4_clockevent_init();
-}
-
-static void __init mct_init_dt(struct device_node *np, unsigned int int_type)
-{
- u32 nr_irqs, i;
-
- mct_int_type = int_type;
-
- /* This driver uses only one global timer interrupt */
- mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ);
+ if ((soc_is_exynos4210()) || (soc_is_exynos5250()))
+ mct_int_type = MCT_INT_SPI;
+ else
+ mct_int_type = MCT_INT_PPI;
- /*
- * Find out the number of local irqs specified. The local
- * timer irqs are specified after the four global timer
- * irqs are specified.
- */
-#ifdef CONFIG_OF
- nr_irqs = of_irq_count(np);
-#else
- nr_irqs = 0;
-#endif
- for (i = MCT_L0_IRQ; i < nr_irqs; i++)
- mct_irqs[i] = irq_of_parse_and_map(np, i);
-
- exynos4_timer_resources(np, of_iomap(np, 0));
+ exynos4_timer_resources();
exynos4_clocksource_init();
exynos4_clockevent_init();
}
-
-
-static void __init mct_init_spi(struct device_node *np)
-{
- return mct_init_dt(np, MCT_INT_SPI);
-}
-
-static void __init mct_init_ppi(struct device_node *np)
-{
- return mct_init_dt(np, MCT_INT_PPI);
-}
-CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi);
-CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi);
diff --git a/trunk/arch/arm/mach-exynos/platsmp.c b/trunk/arch/arm/mach-exynos/platsmp.c
index a0e8ff7758a4..95e04bd5813f 100644
--- a/trunk/arch/arm/mach-exynos/platsmp.c
+++ b/trunk/arch/arm/mach-exynos/platsmp.c
@@ -24,7 +24,6 @@
#include
#include
#include
-#include
#include
#include
@@ -138,21 +137,10 @@ static int __cpuinit exynos_boot_secondary(unsigned int cpu, struct task_struct
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
- unsigned long boot_addr;
-
smp_rmb();
- boot_addr = virt_to_phys(exynos4_secondary_startup);
-
- /*
- * Try to set boot address using firmware first
- * and fall back to boot register if it fails.
- */
- if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
- __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
-
- call_firmware_op(cpu_boot, phys_cpu);
-
+ __raw_writel(virt_to_phys(exynos4_secondary_startup),
+ cpu_boot_reg(phys_cpu));
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
if (pen_release == -1)
@@ -208,20 +196,10 @@ static void __init exynos_smp_prepare_cpus(unsigned int max_cpus)
* system-wide flags register. The boot monitor waits
* until it receives a soft interrupt, and then the
* secondary CPU branches to this address.
- *
- * Try using firmware operation first and fall back to
- * boot register if it fails.
*/
- for (i = 1; i < max_cpus; ++i) {
- unsigned long phys_cpu;
- unsigned long boot_addr;
-
- phys_cpu = cpu_logical_map(i);
- boot_addr = virt_to_phys(exynos4_secondary_startup);
-
- if (call_firmware_op(set_cpu_boot_addr, phys_cpu, boot_addr))
- __raw_writel(boot_addr, cpu_boot_reg(phys_cpu));
- }
+ for (i = 1; i < max_cpus; ++i)
+ __raw_writel(virt_to_phys(exynos4_secondary_startup),
+ cpu_boot_reg(cpu_logical_map(i)));
}
struct smp_operations exynos_smp_ops __initdata = {
diff --git a/trunk/arch/arm/mach-exynos/smc.h b/trunk/arch/arm/mach-exynos/smc.h
deleted file mode 100644
index 13a1dc8ecbf2..000000000000
--- a/trunk/arch/arm/mach-exynos/smc.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (c) 2012 Samsung Electronics.
- *
- * EXYNOS - SMC Call
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_EXYNOS_SMC_H
-#define __ASM_ARCH_EXYNOS_SMC_H
-
-#define SMC_CMD_INIT (-1)
-#define SMC_CMD_INFO (-2)
-/* For Power Management */
-#define SMC_CMD_SLEEP (-3)
-#define SMC_CMD_CPU1BOOT (-4)
-#define SMC_CMD_CPU0AFTR (-5)
-/* For CP15 Access */
-#define SMC_CMD_C15RESUME (-11)
-/* For L2 Cache Access */
-#define SMC_CMD_L2X0CTRL (-21)
-#define SMC_CMD_L2X0SETUP1 (-22)
-#define SMC_CMD_L2X0SETUP2 (-23)
-#define SMC_CMD_L2X0INVALL (-24)
-#define SMC_CMD_L2X0DEBUG (-25)
-
-extern void exynos_smc(u32 cmd, u32 arg1, u32 arg2, u32 arg3);
-
-#endif
diff --git a/trunk/arch/arm/mach-highbank/hotplug.c b/trunk/arch/arm/mach-highbank/hotplug.c
index a019e4e86e51..890cae23c12a 100644
--- a/trunk/arch/arm/mach-highbank/hotplug.c
+++ b/trunk/arch/arm/mach-highbank/hotplug.c
@@ -14,6 +14,7 @@
* this program. If not, see .
*/
#include
+
#include
#include "core.h"
diff --git a/trunk/arch/arm/mach-imx/devices/devices.c b/trunk/arch/arm/mach-imx/devices/devices.c
index 1b4366a0e7c0..1b37482407f9 100644
--- a/trunk/arch/arm/mach-imx/devices/devices.c
+++ b/trunk/arch/arm/mach-imx/devices/devices.c
@@ -37,7 +37,7 @@ int __init mxc_device_init(void)
int ret;
ret = device_register(&mxc_aips_bus);
- if (ret < 0)
+ if (IS_ERR_VALUE(ret))
goto done;
ret = device_register(&mxc_ahb_bus);
diff --git a/trunk/arch/arm/mach-imx/hotplug.c b/trunk/arch/arm/mach-imx/hotplug.c
index 5e91112dcbee..361a253e2b63 100644
--- a/trunk/arch/arm/mach-imx/hotplug.c
+++ b/trunk/arch/arm/mach-imx/hotplug.c
@@ -11,6 +11,7 @@
*/
#include
+#include
#include
#include "common.h"
@@ -19,6 +20,7 @@ static inline void cpu_enter_lowpower(void)
{
unsigned int v;
+ flush_cache_all();
asm volatile(
"mcr p15, 0, %1, c7, c5, 0\n"
" mcr p15, 0, %1, c7, c10, 4\n"
diff --git a/trunk/arch/arm/mach-integrator/integrator_ap.c b/trunk/arch/arm/mach-integrator/integrator_ap.c
index b23c8e4f28e8..ea961445e0e9 100644
--- a/trunk/arch/arm/mach-integrator/integrator_ap.c
+++ b/trunk/arch/arm/mach-integrator/integrator_ap.c
@@ -536,14 +536,16 @@ static void __init ap_init_of(void)
'A' + (ap_sc_id & 0x0f));
soc_dev = soc_device_register(soc_dev_attr);
- if (IS_ERR(soc_dev)) {
+ if (IS_ERR_OR_NULL(soc_dev)) {
kfree(soc_dev_attr->revision);
kfree(soc_dev_attr);
return;
}
parent = soc_device_to_device(soc_dev);
- integrator_init_sysfs(parent, ap_sc_id);
+
+ if (!IS_ERR_OR_NULL(parent))
+ integrator_init_sysfs(parent, ap_sc_id);
of_platform_populate(root, of_default_bus_match_table,
ap_auxdata_lookup, parent);
diff --git a/trunk/arch/arm/mach-integrator/integrator_cp.c b/trunk/arch/arm/mach-integrator/integrator_cp.c
index da1091be0887..2b0db82a5381 100644
--- a/trunk/arch/arm/mach-integrator/integrator_cp.c
+++ b/trunk/arch/arm/mach-integrator/integrator_cp.c
@@ -360,14 +360,17 @@ static void __init intcp_init_of(void)
'A' + (intcp_sc_id & 0x0f));
soc_dev = soc_device_register(soc_dev_attr);
- if (IS_ERR(soc_dev)) {
+ if (IS_ERR_OR_NULL(soc_dev)) {
kfree(soc_dev_attr->revision);
kfree(soc_dev_attr);
return;
}
parent = soc_device_to_device(soc_dev);
- integrator_init_sysfs(parent, intcp_sc_id);
+
+ if (!IS_ERR_OR_NULL(parent))
+ integrator_init_sysfs(parent, intcp_sc_id);
+
of_platform_populate(root, of_default_bus_match_table,
intcp_auxdata_lookup, parent);
}
diff --git a/trunk/arch/arm/mach-kirkwood/Kconfig b/trunk/arch/arm/mach-kirkwood/Kconfig
index 7509a89af967..7b6a64bc5f40 100644
--- a/trunk/arch/arm/mach-kirkwood/Kconfig
+++ b/trunk/arch/arm/mach-kirkwood/Kconfig
@@ -2,96 +2,12 @@ if ARCH_KIRKWOOD
menu "Marvell Kirkwood Implementations"
-config MACH_D2NET_V2
- bool "LaCie d2 Network v2 NAS Board"
- help
- Say 'Y' here if you want your kernel to support the
- LaCie d2 Network v2 NAS.
-
config MACH_DB88F6281_BP
bool "Marvell DB-88F6281-BP Development Board"
help
Say 'Y' here if you want your kernel to support the
Marvell DB-88F6281-BP Development Board.
-config MACH_DOCKSTAR
- bool "Seagate FreeAgent DockStar"
- help
- Say 'Y' here if you want your kernel to support the
- Seagate FreeAgent DockStar.
-
-config MACH_ESATA_SHEEVAPLUG
- bool "Marvell eSATA SheevaPlug Reference Board"
- help
- Say 'Y' here if you want your kernel to support the
- Marvell eSATA SheevaPlug Reference Board.
-
-config MACH_GURUPLUG
- bool "Marvell GuruPlug Reference Board"
- help
- Say 'Y' here if you want your kernel to support the
- Marvell GuruPlug Reference Board.
-
-config MACH_INETSPACE_V2
- bool "LaCie Internet Space v2 NAS Board"
- help
- Say 'Y' here if you want your kernel to support the
- LaCie Internet Space v2 NAS.
-
-config MACH_MV88F6281GTW_GE
- bool "Marvell 88F6281 GTW GE Board"
- help
- Say 'Y' here if you want your kernel to support the
- Marvell 88F6281 GTW GE Board.
-
-config MACH_NET2BIG_V2
- bool "LaCie 2Big Network v2 NAS Board"
- help
- Say 'Y' here if you want your kernel to support the
- LaCie 2Big Network v2 NAS.
-
-config MACH_NET5BIG_V2
- bool "LaCie 5Big Network v2 NAS Board"
- help
- Say 'Y' here if you want your kernel to support the
- LaCie 5Big Network v2 NAS.
-
-config MACH_NETSPACE_MAX_V2
- bool "LaCie Network Space Max v2 NAS Board"
- help
- Say 'Y' here if you want your kernel to support the
- LaCie Network Space Max v2 NAS.
-
-config MACH_NETSPACE_V2
- bool "LaCie Network Space v2 NAS Board"
- help
- Say 'Y' here if you want your kernel to support the
- LaCie Network Space v2 NAS.
-
-config MACH_OPENRD
- bool
-
-config MACH_OPENRD_BASE
- bool "Marvell OpenRD Base Board"
- select MACH_OPENRD
- help
- Say 'Y' here if you want your kernel to support the
- Marvell OpenRD Base Board.
-
-config MACH_OPENRD_CLIENT
- bool "Marvell OpenRD Client Board"
- select MACH_OPENRD
- help
- Say 'Y' here if you want your kernel to support the
- Marvell OpenRD Client Board.
-
-config MACH_OPENRD_ULTIMATE
- bool "Marvell OpenRD Ultimate Board"
- select MACH_OPENRD
- help
- Say 'Y' here if you want your kernel to support the
- Marvell OpenRD Ultimate Board.
-
config MACH_RD88F6192_NAS
bool "Marvell RD-88F6192-NAS Reference Board"
help
@@ -104,33 +20,29 @@ config MACH_RD88F6281
Say 'Y' here if you want your kernel to support the
Marvell RD-88F6281 Reference Board.
-config MACH_SHEEVAPLUG
- bool "Marvell SheevaPlug Reference Board"
+config MACH_MV88F6281GTW_GE
+ bool "Marvell 88F6281 GTW GE Board"
help
Say 'Y' here if you want your kernel to support the
- Marvell SheevaPlug Reference Board.
+ Marvell 88F6281 GTW GE Board.
-config MACH_T5325
- bool "HP t5325 Thin Client"
+config MACH_SHEEVAPLUG
+ bool "Marvell SheevaPlug Reference Board"
help
Say 'Y' here if you want your kernel to support the
- HP t5325 Thin Client.
+ Marvell SheevaPlug Reference Board.
-config MACH_TS219
- bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
+config MACH_ESATA_SHEEVAPLUG
+ bool "Marvell eSATA SheevaPlug Reference Board"
help
Say 'Y' here if you want your kernel to support the
- QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
- TS-219P+ Turbo NAS devices.
+ Marvell eSATA SheevaPlug Reference Board.
-config MACH_TS41X
- bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
+config MACH_GURUPLUG
+ bool "Marvell GuruPlug Reference Board"
help
Say 'Y' here if you want your kernel to support the
- QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
- NAS devices.
-
-comment "Device tree entries"
+ Marvell GuruPlug Reference Board.
config ARCH_KIRKWOOD_DT
bool "Marvell Kirkwood Flattened Device Tree"
@@ -146,27 +58,12 @@ config ARCH_KIRKWOOD_DT
Say 'Y' here if you want your kernel to support the
Marvell Kirkwood using flattened device tree.
-config MACH_CLOUDBOX_DT
- bool "LaCie CloudBox NAS (Flattened Device Tree)"
- select ARCH_KIRKWOOD_DT
- help
- Say 'Y' here if you want your kernel to support the LaCie
- CloudBox NAS, using Flattened Device Tree.
-
-config MACH_DLINK_KIRKWOOD_DT
- bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
- select ARCH_KIRKWOOD_DT
- help
- Say 'Y' here if you want your kernel to support the
- Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
- using Flattened Device Tree.
-
-config MACH_DOCKSTAR_DT
- bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+config MACH_GURUPLUG_DT
+ bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
Say 'Y' here if you want your kernel to support the
- Seagate FreeAgent Dockstar (Flattened Device Tree).
+ Marvell GuruPlug Reference Board (Flattened Device Tree).
config MACH_DREAMPLUG_DT
bool "Marvell DreamPlug (Flattened Device Tree)"
@@ -175,19 +72,19 @@ config MACH_DREAMPLUG_DT
Say 'Y' here if you want your kernel to support the
Marvell DreamPlug (Flattened Device Tree).
-config MACH_GOFLEXNET_DT
- bool "Seagate GoFlex Net (Flattened Device Tree)"
+config MACH_ICONNECT_DT
+ bool "Iomega Iconnect (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
- Say 'Y' here if you want your kernel to support the
- Seagate GoFlex Net (Flattened Device Tree).
+ Say 'Y' here to enable Iomega Iconnect support.
-config MACH_GURUPLUG_DT
- bool "Marvell GuruPlug Reference Board (Flattened Device Tree)"
+config MACH_DLINK_KIRKWOOD_DT
+ bool "D-Link Kirkwood-based NAS (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
Say 'Y' here if you want your kernel to support the
- Marvell GuruPlug Reference Board (Flattened Device Tree).
+ Kirkwood-based D-Link NASes such as DNS-320 & DNS-325,
+ using Flattened Device Tree.
config MACH_IB62X0_DT
bool "RaidSonic IB-NAS6210, IB-NAS6220 (Flattened Device Tree)"
@@ -197,18 +94,41 @@ config MACH_IB62X0_DT
RaidSonic IB-NAS6210 & IB-NAS6220 devices, using
Flattened Device Tree.
-config MACH_ICONNECT_DT
- bool "Iomega Iconnect (Flattened Device Tree)"
+config MACH_TS219_DT
+ bool "Device Tree for QNAP TS-11X, TS-21X NAS"
select ARCH_KIRKWOOD_DT
+ select ARM_APPENDED_DTB
+ select ARM_ATAG_DTB_COMPAT
help
- Say 'Y' here to enable Iomega Iconnect support.
+ Say 'Y' here if you want your kernel to support the QNAP
+ TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
+ TS-219P+ Turbo NAS devices using Fattened Device Tree.
+ There are two different Device Tree descriptions, depending
+ on if the device is based on an if the board uses the MV6281
+ or MV6282. If you have the wrong one, the buttons will not
+ work.
-config MACH_INETSPACE_V2_DT
- bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
+config MACH_DOCKSTAR_DT
+ bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
- Say 'Y' here if you want your kernel to support the LaCie
- Internet Space v2 NAS, using Flattened Device Tree.
+ Say 'Y' here if you want your kernel to support the
+ Seagate FreeAgent Dockstar (Flattened Device Tree).
+
+config MACH_GOFLEXNET_DT
+ bool "Seagate GoFlex Net (Flattened Device Tree)"
+ select ARCH_KIRKWOOD_DT
+ help
+ Say 'Y' here if you want your kernel to support the
+ Seagate GoFlex Net (Flattened Device Tree).
+
+config MACH_LSXL_DT
+ bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
+ select ARCH_KIRKWOOD_DT
+ help
+ Say 'Y' here if you want your kernel to support the
+ Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
+ Flattened Device Tree.
config MACH_IOMEGA_IX2_200_DT
bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
@@ -224,13 +144,12 @@ config MACH_KM_KIRKWOOD_DT
Say 'Y' here if you want your kernel to support the
Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
-config MACH_LSXL_DT
- bool "Buffalo Linkstation LS-XHL, LS-CHLv2 (Flattened Device Tree)"
+config MACH_INETSPACE_V2_DT
+ bool "LaCie Internet Space v2 NAS (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
- Say 'Y' here if you want your kernel to support the
- Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
- Flattened Device Tree.
+ Say 'Y' here if you want your kernel to support the LaCie
+ Internet Space v2 NAS, using Flattened Device Tree.
config MACH_MPLCEC4_DT
bool "MPL CEC4 (Flattened Device Tree)"
@@ -239,12 +158,12 @@ config MACH_MPLCEC4_DT
Say 'Y' here if you want your kernel to support the
MPL CEC4 (Flattened Device Tree).
-config MACH_NETSPACE_LITE_V2_DT
- bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
+config MACH_NETSPACE_V2_DT
+ bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
Say 'Y' here if you want your kernel to support the LaCie
- Network Space Lite v2 NAS, using Flattened Device Tree.
+ Network Space v2 NAS, using Flattened Device Tree.
config MACH_NETSPACE_MAX_V2_DT
bool "LaCie Network Space Max v2 NAS (Flattened Device Tree)"
@@ -253,32 +172,20 @@ config MACH_NETSPACE_MAX_V2_DT
Say 'Y' here if you want your kernel to support the LaCie
Network Space Max v2 NAS, using Flattened Device Tree.
-config MACH_NETSPACE_MINI_V2_DT
- bool "LaCie Network Space Mini v2 NAS (Flattened Device Tree)"
+config MACH_NETSPACE_LITE_V2_DT
+ bool "LaCie Network Space Lite v2 NAS (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
Say 'Y' here if you want your kernel to support the LaCie
- Network Space Mini v2 NAS using Flattened Device Tree.
-
- This board is embedded in a product named CloudBox, which
- provides automatic backup on a 100GB cloud storage. This
- should not confused with a more recent LaCie NAS also named
- CloudBox. For this last, the disk capacity is 1TB or above.
+ Network Space Lite v2 NAS, using Flattened Device Tree.
-config MACH_NETSPACE_V2_DT
- bool "LaCie Network Space v2 NAS (Flattened Device Tree)"
+config MACH_NETSPACE_MINI_V2_DT
+ bool "LaCie Network Space Mini v2 NAS (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
help
Say 'Y' here if you want your kernel to support the LaCie
- Network Space v2 NAS, using Flattened Device Tree.
-
-config MACH_NSA310_DT
- bool "ZyXEL NSA-310 (Flattened Device Tree)"
- select ARCH_KIRKWOOD_DT
- select ARM_ATAG_DTB_COMPAT
- help
- Say 'Y' here if you want your kernel to support the
- ZyXEL NSA-310 board (Flattened Device Tree).
+ Network Space Mini v2 NAS (aka SafeBox), using Flattened
+ Device Tree.
config MACH_OPENBLOCKS_A6_DT
bool "Plat'Home OpenBlocks A6 (Flattened Device Tree)"
@@ -287,15 +194,6 @@ config MACH_OPENBLOCKS_A6_DT
Say 'Y' here if you want your kernel to support the
Plat'Home OpenBlocks A6 (Flattened Device Tree).
-config MACH_READYNAS_DT
- bool "NETGEAR ReadyNAS Duo v2 (Flattened Device Tree)"
- select ARCH_KIRKWOOD_DT
- select ARM_APPENDED_DTB
- select ARM_ATAG_DTB_COMPAT
- help
- Say 'Y' here if you want your kernel to support the
- NETGEAR ReadyNAS Duo v2 using Fattened Device Tree.
-
config MACH_TOPKICK_DT
bool "USI Topkick (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
@@ -303,19 +201,99 @@ config MACH_TOPKICK_DT
Say 'Y' here if you want your kernel to support the
USI Topkick, using Flattened Device Tree
-config MACH_TS219_DT
- bool "Device Tree for QNAP TS-11X, TS-21X NAS"
+config MACH_TS219
+ bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
+ help
+ Say 'Y' here if you want your kernel to support the
+ QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
+ TS-219P+ Turbo NAS devices.
+
+config MACH_TS41X
+ bool "QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo NAS"
+ help
+ Say 'Y' here if you want your kernel to support the
+ QNAP TS-410, TS-410U, TS-419P, TS-419P+ and TS-419U Turbo
+ NAS devices.
+
+config MACH_DOCKSTAR
+ bool "Seagate FreeAgent DockStar"
+ help
+ Say 'Y' here if you want your kernel to support the
+ Seagate FreeAgent DockStar.
+
+config MACH_OPENRD
+ bool
+
+config MACH_OPENRD_BASE
+ bool "Marvell OpenRD Base Board"
+ select MACH_OPENRD
+ help
+ Say 'Y' here if you want your kernel to support the
+ Marvell OpenRD Base Board.
+
+config MACH_OPENRD_CLIENT
+ bool "Marvell OpenRD Client Board"
+ select MACH_OPENRD
+ help
+ Say 'Y' here if you want your kernel to support the
+ Marvell OpenRD Client Board.
+
+config MACH_OPENRD_ULTIMATE
+ bool "Marvell OpenRD Ultimate Board"
+ select MACH_OPENRD
+ help
+ Say 'Y' here if you want your kernel to support the
+ Marvell OpenRD Ultimate Board.
+
+config MACH_NETSPACE_V2
+ bool "LaCie Network Space v2 NAS Board"
+ help
+ Say 'Y' here if you want your kernel to support the
+ LaCie Network Space v2 NAS.
+
+config MACH_INETSPACE_V2
+ bool "LaCie Internet Space v2 NAS Board"
+ help
+ Say 'Y' here if you want your kernel to support the
+ LaCie Internet Space v2 NAS.
+
+config MACH_NETSPACE_MAX_V2
+ bool "LaCie Network Space Max v2 NAS Board"
+ help
+ Say 'Y' here if you want your kernel to support the
+ LaCie Network Space Max v2 NAS.
+
+config MACH_D2NET_V2
+ bool "LaCie d2 Network v2 NAS Board"
+ help
+ Say 'Y' here if you want your kernel to support the
+ LaCie d2 Network v2 NAS.
+
+config MACH_NET2BIG_V2
+ bool "LaCie 2Big Network v2 NAS Board"
+ help
+ Say 'Y' here if you want your kernel to support the
+ LaCie 2Big Network v2 NAS.
+
+config MACH_NET5BIG_V2
+ bool "LaCie 5Big Network v2 NAS Board"
+ help
+ Say 'Y' here if you want your kernel to support the
+ LaCie 5Big Network v2 NAS.
+
+config MACH_T5325
+ bool "HP t5325 Thin Client"
+ help
+ Say 'Y' here if you want your kernel to support the
+ HP t5325 Thin Client.
+
+config MACH_NSA310_DT
+ bool "ZyXEL NSA-310 (Flattened Device Tree)"
select ARCH_KIRKWOOD_DT
- select ARM_APPENDED_DTB
select ARM_ATAG_DTB_COMPAT
help
- Say 'Y' here if you want your kernel to support the QNAP
- TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and
- TS-219P+ Turbo NAS devices using Fattened Device Tree.
- There are two different Device Tree descriptions, depending
- on if the device is based on an if the board uses the MV6281
- or MV6282. If you have the wrong one, the buttons will not
- work.
+ Say 'Y' here if you want your kernel to support the
+ ZyXEL NSA-310 board (Flattened Device Tree).
endmenu
diff --git a/trunk/arch/arm/mach-kirkwood/Makefile b/trunk/arch/arm/mach-kirkwood/Makefile
index cdbca328a412..4cc4bee4d0cf 100644
--- a/trunk/arch/arm/mach-kirkwood/Makefile
+++ b/trunk/arch/arm/mach-kirkwood/Makefile
@@ -1,44 +1,42 @@
obj-y += common.o addr-map.o irq.o pcie.o mpp.o
-obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o
obj-$(CONFIG_MACH_DB88F6281_BP) += db88f6281-bp-setup.o
-obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o
+obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o
+obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o
+obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o
+obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o
obj-$(CONFIG_MACH_ESATA_SHEEVAPLUG) += sheevaplug-setup.o
obj-$(CONFIG_MACH_GURUPLUG) += guruplug-setup.o
+obj-$(CONFIG_MACH_DOCKSTAR) += dockstar-setup.o
+obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o
+obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
+obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o
+obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o
obj-$(CONFIG_MACH_INETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_MV88F6281GTW_GE) += mv88f6281gtw_ge-setup.o
+obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o lacie_v2-common.o
+obj-$(CONFIG_MACH_D2NET_V2) += d2net_v2-setup.o lacie_v2-common.o
obj-$(CONFIG_MACH_NET2BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
obj-$(CONFIG_MACH_NET5BIG_V2) += netxbig_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_NETSPACE_MAX_V2) += netspace_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_NETSPACE_V2) += netspace_v2-setup.o lacie_v2-common.o
-obj-$(CONFIG_MACH_OPENRD) += openrd-setup.o
-obj-$(CONFIG_MACH_RD88F6192_NAS) += rd88f6192-nas-setup.o
-obj-$(CONFIG_MACH_RD88F6281) += rd88f6281-setup.o
-obj-$(CONFIG_MACH_SHEEVAPLUG) += sheevaplug-setup.o
obj-$(CONFIG_MACH_T5325) += t5325-setup.o
-obj-$(CONFIG_MACH_TS219) += ts219-setup.o tsx1x-common.o
-obj-$(CONFIG_MACH_TS41X) += ts41x-setup.o tsx1x-common.o
obj-$(CONFIG_ARCH_KIRKWOOD_DT) += board-dt.o
-obj-$(CONFIG_MACH_CLOUDBOX_DT) += board-ns2.o
-obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o
-obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o
obj-$(CONFIG_MACH_DREAMPLUG_DT) += board-dreamplug.o
-obj-$(CONFIG_MACH_GOFLEXNET_DT) += board-goflexnet.o
obj-$(CONFIG_MACH_GURUPLUG_DT) += board-guruplug.o
-obj-$(CONFIG_MACH_IB62X0_DT) += board-ib62x0.o
obj-$(CONFIG_MACH_ICONNECT_DT) += board-iconnect.o
-obj-$(CONFIG_MACH_INETSPACE_V2_DT) += board-ns2.o
+obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT) += board-dnskw.o
+obj-$(CONFIG_MACH_IB62X0_DT) += board-ib62x0.o
+obj-$(CONFIG_MACH_TS219_DT) += board-ts219.o tsx1x-common.o
+obj-$(CONFIG_MACH_DOCKSTAR_DT) += board-dockstar.o
+obj-$(CONFIG_MACH_GOFLEXNET_DT) += board-goflexnet.o
+obj-$(CONFIG_MACH_LSXL_DT) += board-lsxl.o
obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT) += board-iomega_ix2_200.o
obj-$(CONFIG_MACH_KM_KIRKWOOD_DT) += board-km_kirkwood.o
-obj-$(CONFIG_MACH_LSXL_DT) += board-lsxl.o
+obj-$(CONFIG_MACH_INETSPACE_V2_DT) += board-ns2.o
obj-$(CONFIG_MACH_MPLCEC4_DT) += board-mplcec4.o
-obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT) += board-ns2.o
+obj-$(CONFIG_MACH_NETSPACE_V2_DT) += board-ns2.o
obj-$(CONFIG_MACH_NETSPACE_MAX_V2_DT) += board-ns2.o
+obj-$(CONFIG_MACH_NETSPACE_LITE_V2_DT) += board-ns2.o
obj-$(CONFIG_MACH_NETSPACE_MINI_V2_DT) += board-ns2.o
-obj-$(CONFIG_MACH_NETSPACE_V2_DT) += board-ns2.o
obj-$(CONFIG_MACH_NSA310_DT) += board-nsa310.o
obj-$(CONFIG_MACH_OPENBLOCKS_A6_DT) += board-openblocks_a6.o
-obj-$(CONFIG_MACH_READYNAS_DT) += board-readynas.o
obj-$(CONFIG_MACH_TOPKICK_DT) += board-usi_topkick.o
-obj-$(CONFIG_MACH_TS219_DT) += board-ts219.o tsx1x-common.o
diff --git a/trunk/arch/arm/mach-kirkwood/board-dt.c b/trunk/arch/arm/mach-kirkwood/board-dt.c
index 7904758e771f..d367aa6b47bb 100644
--- a/trunk/arch/arm/mach-kirkwood/board-dt.c
+++ b/trunk/arch/arm/mach-kirkwood/board-dt.c
@@ -139,20 +139,16 @@ static void __init kirkwood_dt_init(void)
if (of_machine_is_compatible("keymile,km_kirkwood"))
km_kirkwood_init();
- if (of_machine_is_compatible("lacie,cloudbox") ||
- of_machine_is_compatible("lacie,inetspace_v2") ||
- of_machine_is_compatible("lacie,netspace_lite_v2") ||
+ if (of_machine_is_compatible("lacie,inetspace_v2") ||
+ of_machine_is_compatible("lacie,netspace_v2") ||
of_machine_is_compatible("lacie,netspace_max_v2") ||
- of_machine_is_compatible("lacie,netspace_mini_v2") ||
- of_machine_is_compatible("lacie,netspace_v2"))
+ of_machine_is_compatible("lacie,netspace_lite_v2") ||
+ of_machine_is_compatible("lacie,netspace_mini_v2"))
ns2_init();
if (of_machine_is_compatible("mpl,cec4"))
mplcec4_init();
- if (of_machine_is_compatible("netgear,readynas-duo-v2"))
- netgear_readynas_init();
-
if (of_machine_is_compatible("plathome,openblocks-a6"))
openblocks_a6_init();
@@ -175,14 +171,12 @@ static const char * const kirkwood_dt_board_compat[] = {
"buffalo,lsxl",
"iom,ix2-200",
"keymile,km_kirkwood",
- "lacie,cloudbox",
"lacie,inetspace_v2",
- "lacie,netspace_lite_v2",
"lacie,netspace_max_v2",
- "lacie,netspace_mini_v2",
"lacie,netspace_v2",
+ "lacie,netspace_lite_v2",
+ "lacie,netspace_mini_v2",
"mpl,cec4",
- "netgear,readynas-duo-v2",
"plathome,openblocks-a6",
"usi,topkick",
"zyxel,nsa310",
diff --git a/trunk/arch/arm/mach-kirkwood/board-ns2.c b/trunk/arch/arm/mach-kirkwood/board-ns2.c
index f8f660525ace..f2ea3b7ad726 100644
--- a/trunk/arch/arm/mach-kirkwood/board-ns2.c
+++ b/trunk/arch/arm/mach-kirkwood/board-ns2.c
@@ -27,8 +27,7 @@ void __init ns2_init(void)
/*
* Basic setup. Needs to be called early.
*/
- if (of_machine_is_compatible("lacie,cloudbox") ||
- of_machine_is_compatible("lacie,netspace_lite_v2") ||
+ if (of_machine_is_compatible("lacie,netspace_lite_v2") ||
of_machine_is_compatible("lacie,netspace_mini_v2"))
ns2_ge00_data.phy_addr = MV643XX_ETH_PHY_ADDR(0);
kirkwood_ge00_init(&ns2_ge00_data);
diff --git a/trunk/arch/arm/mach-kirkwood/board-readynas.c b/trunk/arch/arm/mach-kirkwood/board-readynas.c
deleted file mode 100644
index fb42c20e273f..000000000000
--- a/trunk/arch/arm/mach-kirkwood/board-readynas.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * NETGEAR ReadyNAS Duo v2 Board setup for drivers not already
- * converted to DT.
- *
- * Copyright (C) 2013, Arnaud EBALARD
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-#include
-#include
-#include
-#include