From f9a5999a7b4f99ec3dc9eaaa18d13b152f077da3 Mon Sep 17 00:00:00 2001 From: Daniel Vetter Date: Sat, 31 Mar 2012 11:21:57 +0200 Subject: [PATCH] --- yaml --- r: 298997 b: refs/heads/master c: 80e829fade4eea5f07c410df6a551c42e2d0ca9c h: refs/heads/master i: 298995: 234348bdb3c06955063f80be55706db2ccc0bf50 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/i915/i915_reg.h | 3 +++ trunk/drivers/gpu/drm/i915/intel_display.c | 4 ++++ 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index e5f56c769ba5..a64dd1253899 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 27c1cbd06a7620b354cbb363834f3bb8df4f410d +refs/heads/master: 80e829fade4eea5f07c410df6a551c42e2d0ca9c diff --git a/trunk/drivers/gpu/drm/i915/i915_reg.h b/trunk/drivers/gpu/drm/i915/i915_reg.h index 2abf4eb94039..b4bb1ef77ddc 100644 --- a/trunk/drivers/gpu/drm/i915/i915_reg.h +++ b/trunk/drivers/gpu/drm/i915/i915_reg.h @@ -3728,6 +3728,9 @@ #define GT_FIFO_FREE_ENTRIES 0x120008 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 +#define GEN6_UCGCTL1 0x9400 +# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) + #define GEN6_UCGCTL2 0x9404 # define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) # define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) diff --git a/trunk/drivers/gpu/drm/i915/intel_display.c b/trunk/drivers/gpu/drm/i915/intel_display.c index f446e66cbdaf..bae38acf44dc 100644 --- a/trunk/drivers/gpu/drm/i915/intel_display.c +++ b/trunk/drivers/gpu/drm/i915/intel_display.c @@ -8556,6 +8556,10 @@ static void gen6_init_clock_gating(struct drm_device *dev) I915_WRITE(WM2_LP_ILK, 0); I915_WRITE(WM1_LP_ILK, 0); + I915_WRITE(GEN6_UCGCTL1, + I915_READ(GEN6_UCGCTL1) | + GEN6_BLBUNIT_CLOCK_GATE_DISABLE); + /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock * gating disable must be set. Failure to set it results in * flickering pixels due to Z write ordering failures after