From fa1f93c0e57965262ca5fcd026d275bcf3730c49 Mon Sep 17 00:00:00 2001 From: Alex Deucher Date: Tue, 27 Oct 2009 11:16:09 -0400 Subject: [PATCH] --- yaml --- r: 168474 b: refs/heads/master c: 8f552a66a40bcc6e903e91310f42fe140e0342c4 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/radeon/radeon_atombios.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 24bf86b4fb3f..4868d88ee188 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 3e5cb98dfe87cc61d0a1119dd8aa2b1e4cfab424 +refs/heads/master: 8f552a66a40bcc6e903e91310f42fe140e0342c4 diff --git a/trunk/drivers/gpu/drm/radeon/radeon_atombios.c b/trunk/drivers/gpu/drm/radeon/radeon_atombios.c index 18729259c2fc..1c9a9c461762 100644 --- a/trunk/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/trunk/drivers/gpu/drm/radeon/radeon_atombios.c @@ -655,6 +655,16 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) p1pll->pll_out_min = 64800; else p1pll->pll_out_min = 20000; + } else if (p1pll->pll_out_min > 64800) { + /* Limiting the pll output range is a good thing generally as + * it limits the number of possible pll combinations for a given + * frequency presumably to the ones that work best on each card. + * However, certain duallink DVI monitors seem to like + * pll combinations that would be limited by this at least on + * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per + * family. + */ + p1pll->pll_out_min = 64800; } p1pll->pll_in_min =