From fbe173a005a3023ac251a3e8d802549ad2c2d1b7 Mon Sep 17 00:00:00 2001 From: Robert Richter Date: Tue, 7 Aug 2012 19:43:15 +0200 Subject: [PATCH] --- yaml --- r: 323644 b: refs/heads/master c: 75bc5ca89827fe3f2399321b2920a30bcf658049 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/tools/perf/Documentation/perf-list.txt | 6 ++++++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 212fac70b4e6..7a461407af0d 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 0cf260131c52f681533d17db6fd07545a3dc184e +refs/heads/master: 75bc5ca89827fe3f2399321b2920a30bcf658049 diff --git a/trunk/tools/perf/Documentation/perf-list.txt b/trunk/tools/perf/Documentation/perf-list.txt index ddc22525228d..232be519580a 100644 --- a/trunk/tools/perf/Documentation/perf-list.txt +++ b/trunk/tools/perf/Documentation/perf-list.txt @@ -15,6 +15,7 @@ DESCRIPTION This command displays the symbolic event types which can be selected in the various perf commands with the -e option. +[[EVENT_MODIFIERS]] EVENT MODIFIERS --------------- @@ -44,6 +45,11 @@ layout of IA32_PERFEVTSELx MSRs (see [Intel® 64 and IA-32 Architectures Softwar of IA32_PERFEVTSELx MSRs) or AMD's PerfEvtSeln (see [AMD64 Architecture Programmer’s Manual Volume 2: System Programming], Page 344, Figure 13-7 Performance Event-Select Register (PerfEvtSeln)). +Note: Only the following bit fields can be set in x86 counter +registers: event, umask, edge, inv, cmask. Esp. guest/host only and +OS/user mode flags must be setup using <>. + Example: If the Intel docs for a QM720 Core i7 describe an event as: