diff --git a/[refs] b/[refs]
index f3ac3ab2d1be..0213d115174c 100644
--- a/[refs]
+++ b/[refs]
@@ -1,2 +1,2 @@
 ---
-refs/heads/master: edd6bcd8209c31b91e1fbc112a756475091c483d
+refs/heads/master: f5430f93257d336346a9018c915e879ce43f5f89
diff --git a/trunk/include/asm-x86/pgalloc_32.h b/trunk/include/asm-x86/pgalloc_32.h
index 7641e7b5d931..6c21ef951dab 100644
--- a/trunk/include/asm-x86/pgalloc_32.h
+++ b/trunk/include/asm-x86/pgalloc_32.h
@@ -80,8 +80,10 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd)
 	set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT));
 
 	/*
-	 * Pentium-II erratum A13: in PAE mode we explicitly have to flush
-	 * the TLB via cr3 if the top-level pgd is changed...
+	 * According to Intel App note "TLBs, Paging-Structure Caches,
+	 * and Their Invalidation", April 2007, document 317080-001,
+	 * section 8.1: in PAE mode we explicitly have to flush the
+	 * TLB via cr3 if the top-level pgd is changed...
 	 */
 	if (mm == current->active_mm)
 		write_cr3(read_cr3());
diff --git a/trunk/include/asm-x86/pgtable-3level.h b/trunk/include/asm-x86/pgtable-3level.h
index ad71960bca3a..1d763eec740f 100644
--- a/trunk/include/asm-x86/pgtable-3level.h
+++ b/trunk/include/asm-x86/pgtable-3level.h
@@ -98,8 +98,10 @@ static inline void pud_clear(pud_t *pudp)
 	set_pud(pudp, __pud(0));
 
 	/*
-	 * Pentium-II erratum A13: in PAE mode we explicitly have to flush
-	 * the TLB via cr3 if the top-level pgd is changed...
+	 * According to Intel App note "TLBs, Paging-Structure Caches,
+	 * and Their Invalidation", April 2007, document 317080-001,
+	 * section 8.1: in PAE mode we explicitly have to flush the
+	 * TLB via cr3 if the top-level pgd is changed...
 	 *
 	 * Make sure the pud entry we're updating is within the
 	 * current pgd to avoid unnecessary TLB flushes.