From fc7ff499d0bc03a86e106c8e5167f6f3549bf12d Mon Sep 17 00:00:00 2001 From: Jeremy Fitzhardinge Date: Mon, 4 Feb 2008 16:48:02 +0100 Subject: [PATCH] --- yaml --- r: 82871 b: refs/heads/master c: f5430f93257d336346a9018c915e879ce43f5f89 h: refs/heads/master i: 82869: c531ab9d93b9cba0331309e5b3de8e275f01acb8 82867: 66bb12e489a6e5229db76268bafb4575565dca31 82863: 2e371dbedb078a2c4b8b3c5306aee31c2c4318c1 v: v3 --- [refs] | 2 +- trunk/include/asm-x86/pgalloc_32.h | 6 ++++-- trunk/include/asm-x86/pgtable-3level.h | 6 ++++-- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/[refs] b/[refs] index f3ac3ab2d1be..0213d115174c 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: edd6bcd8209c31b91e1fbc112a756475091c483d +refs/heads/master: f5430f93257d336346a9018c915e879ce43f5f89 diff --git a/trunk/include/asm-x86/pgalloc_32.h b/trunk/include/asm-x86/pgalloc_32.h index 7641e7b5d931..6c21ef951dab 100644 --- a/trunk/include/asm-x86/pgalloc_32.h +++ b/trunk/include/asm-x86/pgalloc_32.h @@ -80,8 +80,10 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pudp, pmd_t *pmd) set_pud(pudp, __pud(__pa(pmd) | _PAGE_PRESENT)); /* - * Pentium-II erratum A13: in PAE mode we explicitly have to flush - * the TLB via cr3 if the top-level pgd is changed... + * According to Intel App note "TLBs, Paging-Structure Caches, + * and Their Invalidation", April 2007, document 317080-001, + * section 8.1: in PAE mode we explicitly have to flush the + * TLB via cr3 if the top-level pgd is changed... */ if (mm == current->active_mm) write_cr3(read_cr3()); diff --git a/trunk/include/asm-x86/pgtable-3level.h b/trunk/include/asm-x86/pgtable-3level.h index ad71960bca3a..1d763eec740f 100644 --- a/trunk/include/asm-x86/pgtable-3level.h +++ b/trunk/include/asm-x86/pgtable-3level.h @@ -98,8 +98,10 @@ static inline void pud_clear(pud_t *pudp) set_pud(pudp, __pud(0)); /* - * Pentium-II erratum A13: in PAE mode we explicitly have to flush - * the TLB via cr3 if the top-level pgd is changed... + * According to Intel App note "TLBs, Paging-Structure Caches, + * and Their Invalidation", April 2007, document 317080-001, + * section 8.1: in PAE mode we explicitly have to flush the + * TLB via cr3 if the top-level pgd is changed... * * Make sure the pud entry we're updating is within the * current pgd to avoid unnecessary TLB flushes.