From fdbe92f80f52428bfb6de0d489bbeef49df1e833 Mon Sep 17 00:00:00 2001 From: Vaibhav Hiremath Date: Wed, 27 Mar 2013 15:34:26 +0530 Subject: [PATCH] --- yaml --- r: 376215 b: refs/heads/master c: a6d25f4c951b8b28f2eaec6f891ff834622532f2 h: refs/heads/master i: 376213: b19ab2a12a3555a7baa5919c3790a5ef6cd3dc8d 376211: 1bfba410052c90356d0483924c4326450e44423f 376207: 26ff1d76c2618b09143656581b4be098072e8e30 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-omap2/cclock33xx_data.c | 26 ++++++++++++++++++--- 2 files changed, 24 insertions(+), 4 deletions(-) diff --git a/[refs] b/[refs] index 5c9dd99cf5c9..c633d03cc6af 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: a545ec160afea245939290e7f616f68de906a85c +refs/heads/master: a6d25f4c951b8b28f2eaec6f891ff834622532f2 diff --git a/trunk/arch/arm/mach-omap2/cclock33xx_data.c b/trunk/arch/arm/mach-omap2/cclock33xx_data.c index 6ebc7803bc3e..af3544ce4f02 100644 --- a/trunk/arch/arm/mach-omap2/cclock33xx_data.c +++ b/trunk/arch/arm/mach-omap2/cclock33xx_data.c @@ -454,9 +454,29 @@ DEFINE_CLK_GATE(cefuse_fck, "sys_clkin_ck", &sys_clkin_ck, 0x0, */ DEFINE_CLK_FIXED_FACTOR(clkdiv32k_ck, "clk_24mhz", &clk_24mhz, 0x0, 1, 732); -DEFINE_CLK_GATE(clkdiv32k_ick, "clkdiv32k_ck", &clkdiv32k_ck, 0x0, - AM33XX_CM_PER_CLKDIV32K_CLKCTRL, AM33XX_MODULEMODE_SWCTRL_SHIFT, - 0x0, NULL); +static struct clk clkdiv32k_ick; + +static const char *clkdiv32k_ick_parent_names[] = { + "clkdiv32k_ck", +}; + +static const struct clk_ops clkdiv32k_ick_ops = { + .enable = &omap2_dflt_clk_enable, + .disable = &omap2_dflt_clk_disable, + .is_enabled = &omap2_dflt_clk_is_enabled, + .init = &omap2_init_clk_clkdm, +}; + +static struct clk_hw_omap clkdiv32k_ick_hw = { + .hw = { + .clk = &clkdiv32k_ick, + }, + .enable_reg = AM33XX_CM_PER_CLKDIV32K_CLKCTRL, + .enable_bit = AM33XX_MODULEMODE_SWCTRL_SHIFT, + .clkdm_name = "clk_24mhz_clkdm", +}; + +DEFINE_STRUCT_CLK(clkdiv32k_ick, clkdiv32k_ick_parent_names, clkdiv32k_ick_ops); /* "usbotg_fck" is an additional clock and not really a modulemode */ DEFINE_CLK_GATE(usbotg_fck, "dpll_per_ck", &dpll_per_ck, 0x0,