From fdc96d0799397e748847fb6b244320f662a24de2 Mon Sep 17 00:00:00 2001 From: Martin Fuzzey Date: Tue, 29 Jan 2013 16:46:12 +0100 Subject: [PATCH] --- yaml --- r: 359807 b: refs/heads/master c: f1550a1ce79f1424beca55e78122e594f5ef9094 h: refs/heads/master i: 359805: dca2078fc5dcc44945477ee53fbeb7eb71695144 359803: 11d8dae12a62e67d26040a04650e104fe05d4d6b 359799: ecd0be5a2ee0cbab678fbc585f756d63fd62d195 359791: 3a2210f8b1e8f66fc698aa6f480ce0f68e2868ce 359775: 2a8828de96173ed2bd129ce5916b35ac5e5f87fd 359743: feda94258ab8682e3ee952551cb07f507ac295c5 359679: ed40ea89f9ee9578e786f6e579bba77d537f7190 v: v3 --- [refs] | 2 +- trunk/Documentation/devicetree/bindings/clock/imx5-clock.txt | 1 + trunk/arch/arm/mach-imx/clk-imx51-imx53.c | 4 +++- 3 files changed, 5 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index f1ae257d1ce7..2101abd9d4b1 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 28c55dc1acc863cb29832b5be2464ebcdafdc3d5 +refs/heads/master: f1550a1ce79f1424beca55e78122e594f5ef9094 diff --git a/trunk/Documentation/devicetree/bindings/clock/imx5-clock.txt b/trunk/Documentation/devicetree/bindings/clock/imx5-clock.txt index 04ad47876be0..2a0c904c46ae 100644 --- a/trunk/Documentation/devicetree/bindings/clock/imx5-clock.txt +++ b/trunk/Documentation/devicetree/bindings/clock/imx5-clock.txt @@ -171,6 +171,7 @@ clocks and IDs. can_sel 156 can1_serial_gate 157 can1_ipg_gate 158 + owire_gate 159 Examples (for mx53): diff --git a/trunk/arch/arm/mach-imx/clk-imx51-imx53.c b/trunk/arch/arm/mach-imx/clk-imx51-imx53.c index fb7cb841b64c..0f39f8c93b94 100644 --- a/trunk/arch/arm/mach-imx/clk-imx51-imx53.c +++ b/trunk/arch/arm/mach-imx/clk-imx51-imx53.c @@ -83,6 +83,7 @@ enum imx5_clks { ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate, epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate, can_sel, can1_serial_gate, can1_ipg_gate, + owire_gate, clk_max }; @@ -233,12 +234,13 @@ static void __init mx5_clocks_common_init(unsigned long rate_ckil, clk[epit1_hf_gate] = imx_clk_gate2("epit1_hf_gate", "per_root", MXC_CCM_CCGR2, 4); clk[epit2_ipg_gate] = imx_clk_gate2("epit2_ipg_gate", "ipg", MXC_CCM_CCGR2, 6); clk[epit2_hf_gate] = imx_clk_gate2("epit2_hf_gate", "per_root", MXC_CCM_CCGR2, 8); + clk[owire_gate] = imx_clk_gate2("owire_gate", "per_root", MXC_CCM_CCGR2, 22); for (i = 0; i < ARRAY_SIZE(clk); i++) if (IS_ERR(clk[i])) pr_err("i.MX5 clk %d: register failed with %ld\n", i, PTR_ERR(clk[i])); - + clk_register_clkdev(clk[gpt_hf_gate], "per", "imx-gpt.0"); clk_register_clkdev(clk[gpt_ipg_gate], "ipg", "imx-gpt.0"); clk_register_clkdev(clk[uart1_per_gate], "per", "imx21-uart.0");