From fe8f69e46155a8ec43e872ed70df3e1c592341ea Mon Sep 17 00:00:00 2001 From: Eric Miao Date: Fri, 28 Nov 2008 14:54:39 +0800 Subject: [PATCH] --- yaml --- r: 123663 b: refs/heads/master c: f1647e4c068139b5f6c988b0862eb1d233dfffe2 h: refs/heads/master i: 123661: aed842130a7737323bb49bc0f75f59311f8b7e7c 123659: ea36201fd8d0db64a11753fc27f1e1e2beb9f9a4 123655: 51e155c36c9f888e124ddf4be0ac36347fbc0887 123647: 7f95134b629547e4b10c0fc355f2a61cc2219bb6 v: v3 --- [refs] | 2 +- trunk/arch/arm/mach-pxa/gpio.c | 12 ++++++++ .../arch/arm/mach-pxa/include/mach/pxa-regs.h | 28 ------------------- 3 files changed, 13 insertions(+), 29 deletions(-) diff --git a/[refs] b/[refs] index dc797e4f3e30..2b54a4ae3d88 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 1f017a9964c5b3b9581d3a5732110cb1e0444281 +refs/heads/master: f1647e4c068139b5f6c988b0862eb1d233dfffe2 diff --git a/trunk/arch/arm/mach-pxa/gpio.c b/trunk/arch/arm/mach-pxa/gpio.c index 843144ff1f61..5fec1e479cb3 100644 --- a/trunk/arch/arm/mach-pxa/gpio.c +++ b/trunk/arch/arm/mach-pxa/gpio.c @@ -25,6 +25,18 @@ #include "generic.h" +#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) +#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) +#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) +#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) + +#define GPLR_OFFSET 0x00 +#define GPDR_OFFSET 0x0C +#define GPSR_OFFSET 0x18 +#define GPCR_OFFSET 0x24 +#define GRER_OFFSET 0x30 +#define GFER_OFFSET 0x3C +#define GEDR_OFFSET 0x48 struct pxa_gpio_chip { struct gpio_chip chip; diff --git a/trunk/arch/arm/mach-pxa/include/mach/pxa-regs.h b/trunk/arch/arm/mach-pxa/include/mach/pxa-regs.h index a56502898030..782ad4ab8055 100644 --- a/trunk/arch/arm/mach-pxa/include/mach/pxa-regs.h +++ b/trunk/arch/arm/mach-pxa/include/mach/pxa-regs.h @@ -203,19 +203,6 @@ * General Purpose I/O */ -#define GPIO0_BASE ((void __iomem *)io_p2v(0x40E00000)) -#define GPIO1_BASE ((void __iomem *)io_p2v(0x40E00004)) -#define GPIO2_BASE ((void __iomem *)io_p2v(0x40E00008)) -#define GPIO3_BASE ((void __iomem *)io_p2v(0x40E00100)) - -#define GPLR_OFFSET 0x00 -#define GPDR_OFFSET 0x0C -#define GPSR_OFFSET 0x18 -#define GPCR_OFFSET 0x24 -#define GRER_OFFSET 0x30 -#define GFER_OFFSET 0x3C -#define GEDR_OFFSET 0x48 - #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */ #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */ #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */ @@ -265,10 +252,6 @@ #define GPIO_bit(x) (1 << ((x) & 0x1f)) -#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx) - -/* Interrupt Controller */ - #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) @@ -287,18 +270,7 @@ #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3)) #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \ ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U))) -#else - -#define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3) -#define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3) -#define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3) -#define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3) -#define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3) -#define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3) -#define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3) -#define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2) -#endif /* * Power Manager - see pxa2xx-regs.h