From feb446c1b7eaedb574bfe7c5c08111a470a8ea83 Mon Sep 17 00:00:00 2001 From: Varun Sethi Date: Tue, 20 Nov 2012 19:24:55 +0530 Subject: [PATCH] --- yaml --- r: 346830 b: refs/heads/master c: 5320b50797a9a5373f31f5b1c26346357f73e179 h: refs/heads/master v: v3 --- [refs] | 2 +- trunk/arch/powerpc/include/asm/fsl_guts.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index f4f42705c17c..797af8191070 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: bc15236fbed1e017b465e38a9d2092393778a2f7 +refs/heads/master: 5320b50797a9a5373f31f5b1c26346357f73e179 diff --git a/trunk/arch/powerpc/include/asm/fsl_guts.h b/trunk/arch/powerpc/include/asm/fsl_guts.h index dd5ba2c22771..77ced0b3d81d 100644 --- a/trunk/arch/powerpc/include/asm/fsl_guts.h +++ b/trunk/arch/powerpc/include/asm/fsl_guts.h @@ -71,7 +71,9 @@ struct ccsr_guts { u8 res0c4[0x224 - 0xc4]; __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */ __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */ - u8 res22c[0x800 - 0x22c]; + u8 res22c[0x604 - 0x22c]; + __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */ + u8 res608[0x800 - 0x608]; __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */ u8 res804[0x900 - 0x804]; __be32 ircr; /* 0x.0900 - Infrared Control Register */