From feeec41dc9b09ed009a4ed865bf2498ced13ce27 Mon Sep 17 00:00:00 2001 From: Bartlomiej Zolnierkiewicz Date: Wed, 4 Nov 2009 18:32:32 +0100 Subject: [PATCH] --- yaml --- r: 171405 b: refs/heads/master c: 8807bb8cddbeb5b48bd9c6e40396af07980c7cdf h: refs/heads/master i: 171403: dc6a69e6751b91d63851dbdeb833aed1eeb3cdcc v: v3 --- [refs] | 2 +- trunk/drivers/net/wireless/rt2x00/rt2800pci.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/[refs] b/[refs] index f5e45bf472c5..28ab8490de5b 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: f644fea1a8433f65f78a36cd7b23b8f57b0f77e4 +refs/heads/master: 8807bb8cddbeb5b48bd9c6e40396af07980c7cdf diff --git a/trunk/drivers/net/wireless/rt2x00/rt2800pci.c b/trunk/drivers/net/wireless/rt2x00/rt2800pci.c index 5b3f40356c64..e4a1a858a2fd 100644 --- a/trunk/drivers/net/wireless/rt2x00/rt2800pci.c +++ b/trunk/drivers/net/wireless/rt2x00/rt2800pci.c @@ -56,8 +56,10 @@ MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); /* * Register access. + * All access to the CSR registers will go through the methods + * rt2x00pci_register_read and rt2x00pci_register_write. * BBP and RF register require indirect register access, - * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this. + * and use the CSR registers BBPCSR and RFCSR to achieve this. * These indirect registers work with busy bits, * and we will try maximal REGISTER_BUSY_COUNT times to access * the register while taking a REGISTER_BUSY_DELAY us delay