From ff784dae9879cbd732351cc98bed3c9f3889a6fd Mon Sep 17 00:00:00 2001 From: Ben Skeggs Date: Mon, 6 Feb 2012 11:42:29 +1000 Subject: [PATCH] --- yaml --- r: 307523 b: refs/heads/master c: a94ba1fcac417d0b72f73fb77e730279ca9203c3 h: refs/heads/master i: 307521: 1cb3cd1e21dbbfaf966f79bcd630ccce17591291 307519: 1a881a7da1c92df2d8c5e7406f7db56f7c1ad533 v: v3 --- [refs] | 2 +- trunk/drivers/gpu/drm/nouveau/nouveau_mem.c | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/[refs] b/[refs] index 05cab769ce14..fbf961f43d52 100644 --- a/[refs] +++ b/[refs] @@ -1,2 +1,2 @@ --- -refs/heads/master: 6b91d6b056ba39633cbdf24b9973df4ac99d7130 +refs/heads/master: a94ba1fcac417d0b72f73fb77e730279ca9203c3 diff --git a/trunk/drivers/gpu/drm/nouveau/nouveau_mem.c b/trunk/drivers/gpu/drm/nouveau/nouveau_mem.c index bb2f0a43f590..ec4c53f41171 100644 --- a/trunk/drivers/gpu/drm/nouveau/nouveau_mem.c +++ b/trunk/drivers/gpu/drm/nouveau/nouveau_mem.c @@ -843,6 +843,7 @@ nouveau_mem_timing_calc(struct drm_device *dev, u32 freq, ret = nv50_mem_timing_calc(dev, freq, e, len, boot, t); break; case NV_C0: + case NV_D0: ret = nvc0_mem_timing_calc(dev, freq, e, len, boot, t); break; default: