Skip to content
Navigation Menu
Toggle navigation
Sign in
In this repository
All GitHub Enterprise
↵
Jump to
↵
No suggested jump to results
In this repository
All GitHub Enterprise
↵
Jump to
↵
In this organization
All GitHub Enterprise
↵
Jump to
↵
In this repository
All GitHub Enterprise
↵
Jump to
↵
Sign in
Reseting focus
You signed in with another tab or window.
Reload
to refresh your session.
You signed out in another tab or window.
Reload
to refresh your session.
You switched accounts on another tab or window.
Reload
to refresh your session.
Dismiss alert
{{ message }}
mariux64
/
linux
Public
Notifications
You must be signed in to change notification settings
Fork
0
Star
0
Code
Issues
2
Pull requests
0
Actions
Projects
0
Wiki
Security
Insights
Additional navigation options
Code
Issues
Pull requests
Actions
Projects
Wiki
Security
Insights
Files
77a5c59
Documentation
arch
alpha
arc
arm
arm64
avr32
blackfin
c6x
cris
frv
hexagon
ia64
m32r
m68k
metag
microblaze
mips
alchemy
ar7
ath25
ath79
bcm3384
bcm47xx
bcm63xx
boot
cavium-octeon
cobalt
configs
dec
emma
fw
include
asm
dec
emma
fw
ip32
lasat
mach-ar7
mach-ath25
mach-ath79
mach-au1x00
mach-bcm3384
mach-bcm47xx
mach-bcm63xx
mach-cavium-octeon
mach-cobalt
mach-db1x00
mach-dec
mach-emma2rh
mach-generic
mach-ip22
mach-ip27
mach-ip28
mach-ip32
mach-jazz
mach-jz4740
mach-lantiq
mach-lasat
mach-loongson
mach-loongson1
mach-malta
mach-netlogic
mach-paravirt
mach-pmcs-msp71xx
mach-pnx833x
mach-ralink
mach-rc32434
mach-rm
mach-sead3
mach-sibyte
mach-tx39xx
mach-tx49xx
mach-vr41xx
mips-boards
netlogic
octeon
pci
sgi
sibyte
sn
txx9
vr41xx
xtalk
Kbuild
abi.h
addrspace.h
amon.h
arch_hweight.h
asm-eva.h
asm-offsets.h
asm.h
asmmacro-32.h
asmmacro-64.h
asmmacro.h
atomic.h
barrier.h
bcache.h
bitops.h
bmips.h
bootinfo.h
branch.h
break.h
bug.h
bugs.h
cache.h
cacheflush.h
cacheops.h
cevt-r4k.h
checksum.h
clkdev.h
clock.h
cmp.h
cmpxchg.h
compat-signal.h
compat.h
compiler.h
cop2.h
cpu-features.h
cpu-info.h
cpu-type.h
cpu.h
debug.h
delay.h
device.h
div64.h
dma-coherence.h
dma-mapping.h
dma.h
ds1287.h
dsp.h
edac.h
elf.h
errno.h
eva.h
exec.h
fb.h
fixmap.h
floppy.h
fpregdef.h
fpu.h
fpu_emulator.h
ftrace.h
futex.h
gio_device.h
gpio.h
gt64120.h
hardirq.h
hazards.h
highmem.h
hpet.h
hugetlb.h
hw_irq.h
i8259.h
ide.h
idle.h
inst.h
io.h
irq.h
irq_cpu.h
irq_gt641xx.h
irq_regs.h
irqflags.h
isadep.h
jazz.h
jazzdma.h
jump_label.h
kdebug.h
kexec.h
kgdb.h
kmap_types.h
kprobes.h
kvm_host.h
kvm_para.h
linkage.h
local.h
m48t37.h
maar.h
mc146818-time.h
mc146818rtc.h
mips-cm.h
mips-cpc.h
mips_machine.h
mips_mt.h
mipsmtregs.h
mipsprom.h
mipsregs.h
mmu.h
mmu_context.h
mmzone.h
module.h
msa.h
msc01_ic.h
nile4.h
paccess.h
page.h
pci.h
perf_event.h
pgalloc.h
pgtable-32.h
pgtable-64.h
pgtable-bits.h
pgtable.h
pm-cps.h
pm.h
pmon.h
prefetch.h
processor.h
prom.h
ptrace.h
r4k-timer.h
r4kcache.h
reboot.h
reg.h
regdef.h
rtlx.h
seccomp.h
setup.h
sgialib.h
sgiarcs.h
shmparam.h
sigcontext.h
siginfo.h
signal.h
sim.h
smp-cps.h
smp-ops.h
smp.h
sni.h
socket.h
sparsemem.h
spinlock.h
spinlock_types.h
spram.h
stackframe.h
stackprotector.h
stacktrace.h
string.h
switch_to.h
syscall.h
termios.h
thread_info.h
time.h
timex.h
tlb.h
tlbdebug.h
tlbflush.h
tlbmisc.h
topology.h
traps.h
txx9irq.h
txx9pio.h
txx9tmr.h
types.h
uaccess.h
uasm.h
unaligned.h
unistd.h
vdso.h
vga.h
vpe.h
war.h
watch.h
wbflush.h
uapi
jazz
jz4740
kernel
kvm
lantiq
lasat
lib
loongson
loongson1
math-emu
mm
mti-malta
mti-sead3
net
netlogic
oprofile
paravirt
pci
pmcs-msp71xx
pnx833x
power
ralink
rb532
sgi-ip22
sgi-ip27
sgi-ip32
sibyte
sni
txx9
vr41xx
Kbuild
Kbuild.platforms
Kconfig
Kconfig.debug
Makefile
mn10300
openrisc
parisc
powerpc
s390
score
sh
sparc
tile
um
unicore32
x86
xtensa
.gitignore
Kconfig
block
crypto
drivers
firmware
fs
include
init
ipc
kernel
lib
mm
net
samples
scripts
security
sound
tools
usr
virt
.gitignore
.mailmap
COPYING
CREDITS
Kbuild
Kconfig
MAINTAINERS
Makefile
README
REPORTING-BUGS
Breadcrumbs
linux
/
arch
/
mips
/
include
/
asm
/
pgtable-32.h
Blame
Blame
Latest commit
History
History
229 lines (185 loc) · 7.35 KB
Breadcrumbs
linux
/
arch
/
mips
/
include
/
asm
/
pgtable-32.h
Top
File metadata and controls
Code
Blame
229 lines (185 loc) · 7.35 KB
Raw
/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc. */ #ifndef _ASM_PGTABLE_32_H #define _ASM_PGTABLE_32_H #include <asm/addrspace.h> #include <asm/page.h> #include <linux/linkage.h> #include <asm/cachectl.h> #include <asm/fixmap.h> #include <asm-generic/pgtable-nopmd.h> extern int temp_tlb_entry __cpuinitdata; /* * - add_temporary_entry() add a temporary TLB entry. We use TLB entries * starting at the top and working down. This is for populating the * TLB before trap_init() puts the TLB miss handler in place. It * should be used only for entries matching the actual page tables, * to prevent inconsistencies. */ extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask); /* * Basically we have the same two-level (which is the logical three level * Linux page table layout folded) page tables as the i386. Some day * when we have proper page coloring support we can have a 1% quicker * tlb refill handling mechanism, but for now it is a bit slower but * works even with the cache aliasing problem the R4k and above have. */ /* PGDIR_SHIFT determines what a third-level page table entry can map */ #define PGDIR_SHIFT (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2) #define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_MASK (~(PGDIR_SIZE-1)) /* * Entries per page directory level: we use two-level, so * we don't really have any PUD/PMD directory physically. */ #define __PGD_ORDER (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2) #define PGD_ORDER (__PGD_ORDER >= 0 ? __PGD_ORDER : 0) #define PUD_ORDER aieeee_attempt_to_allocate_pud #define PMD_ORDER 1 #define PTE_ORDER 0 #define PTRS_PER_PGD (USER_PTRS_PER_PGD * 2) #define PTRS_PER_PTE ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t)) #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE) #define FIRST_USER_ADDRESS 0 #define VMALLOC_START MAP_BASE #define PKMAP_BASE (0xfe000000UL) #ifdef CONFIG_HIGHMEM # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE) #else # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE) #endif #ifdef CONFIG_PHYS_ADDR_T_64BIT #define pte_ERROR(e) \ printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e)) #else #define pte_ERROR(e) \ printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e)) #endif #define pgd_ERROR(e) \ printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e)) extern void load_pgd(unsigned long pg_dir); extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)]; /* * Empty pgd/pmd entries point to the invalid_pte_table. */ static inline int pmd_none(pmd_t pmd) { return pmd_val(pmd) == (unsigned long) invalid_pte_table; } #define pmd_bad(pmd) (pmd_val(pmd) & ~PAGE_MASK) static inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) != (unsigned long) invalid_pte_table; } static inline void pmd_clear(pmd_t *pmdp) { pmd_val(*pmdp) = ((unsigned long) invalid_pte_table); } #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) #define pte_page(x) pfn_to_page(pte_pfn(x)) #define pte_pfn(x) ((unsigned long)((x).pte_high >> 6)) static inline pte_t pfn_pte(unsigned long pfn, pgprot_t prot) { pte_t pte; pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f); pte.pte_low = pgprot_val(prot); return pte; } #else #define pte_page(x) pfn_to_page(pte_pfn(x)) #ifdef CONFIG_CPU_VR41XX #define pte_pfn(x) ((unsigned long)((x).pte >> (PAGE_SHIFT + 2))) #define pfn_pte(pfn, prot) __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot)) #else #define pte_pfn(x) ((unsigned long)((x).pte >> _PFN_SHIFT)) #define pfn_pte(pfn, prot) __pte(((unsigned long long)(pfn) << _PFN_SHIFT) | pgprot_val(prot)) #endif #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */ #define __pgd_offset(address) pgd_index(address) #define __pud_offset(address) (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1)) #define __pmd_offset(address) (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1)) /* to find an entry in a kernel page-table-directory */ #define pgd_offset_k(address) pgd_offset(&init_mm, address) #define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) /* to find an entry in a page-table-directory */ #define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr)) /* Find an entry in the third-level page table.. */ #define __pte_offset(address) \ (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)) #define pte_offset(dir, address) \ ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) #define pte_offset_kernel(dir, address) \ ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address)) #define pte_offset_map(dir, address) \ ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address)) #define pte_unmap(pte) ((void)(pte)) #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) /* Swap entries must have VALID bit cleared. */ #define __swp_type(x) (((x).val >> 10) & 0x1f) #define __swp_offset(x) ((x).val >> 15) #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 10) | ((offset) << 15) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) /* * Encode and decode a nonlinear file mapping entry */ #define pte_to_pgoff(_pte) ((((_pte).pte >> 1 ) & 0x07) | \ (((_pte).pte >> 2 ) & 0x38) | \ (((_pte).pte >> 10) << 6 )) #define pgoff_to_pte(off) ((pte_t) { (((off) & 0x07) << 1 ) | \ (((off) & 0x38) << 2 ) | \ (((off) >> 6 ) << 10) | \ _PAGE_FILE }) /* * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range: */ #define PTE_FILE_MAX_BITS 28 #else #if defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) /* Swap entries must have VALID and GLOBAL bits cleared. */ #define __swp_type(x) (((x).val >> 2) & 0x1f) #define __swp_offset(x) ((x).val >> 7) #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 2) | ((offset) << 7) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high }) #define __swp_entry_to_pte(x) ((pte_t) { 0, (x).val }) /* * Bits 0 and 1 of pte_high are taken, use the rest for the page offset... */ #define pte_to_pgoff(_pte) ((_pte).pte_high >> 2) #define pgoff_to_pte(off) ((pte_t) { _PAGE_FILE, (off) << 2 }) #define PTE_FILE_MAX_BITS 30 #else /* * Constraints: * _PAGE_PRESENT at bit 0 * _PAGE_MODIFIED at bit 4 * _PAGE_GLOBAL at bit 6 * _PAGE_VALID at bit 7 */ #define __swp_type(x) (((x).val >> 8) & 0x1f) #define __swp_offset(x) ((x).val >> 13) #define __swp_entry(type,offset) ((swp_entry_t) { ((type) << 8) | ((offset) << 13) }) #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) }) #define __swp_entry_to_pte(x) ((pte_t) { (x).val }) /* * Encode and decode a nonlinear file mapping entry */ #define pte_to_pgoff(_pte) ((((_pte).pte >> 1) & 0x7) | \ (((_pte).pte >> 2) & 0x8) | \ (((_pte).pte >> 8) << 4)) #define pgoff_to_pte(off) ((pte_t) { (((off) & 0x7) << 1) | \ (((off) & 0x8) << 2) | \ (((off) >> 4) << 8) | \ _PAGE_FILE }) #define PTE_FILE_MAX_BITS 28 #endif /* defined(CONFIG_PHYS_ADDR_T_64BIT) && defined(CONFIG_CPU_MIPS32) */ #endif /* defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX) */ #endif /* _ASM_PGTABLE_32_H */
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
You can’t perform that action at this time.