Skip to content
Navigation Menu
Toggle navigation
Sign in
In this repository
All GitHub Enterprise
↵
Jump to
↵
No suggested jump to results
In this repository
All GitHub Enterprise
↵
Jump to
↵
In this organization
All GitHub Enterprise
↵
Jump to
↵
In this repository
All GitHub Enterprise
↵
Jump to
↵
Sign in
Reseting focus
You signed in with another tab or window.
Reload
to refresh your session.
You signed out in another tab or window.
Reload
to refresh your session.
You switched accounts on another tab or window.
Reload
to refresh your session.
Dismiss alert
{{ message }}
mariux64
/
linux
Public
Notifications
You must be signed in to change notification settings
Fork
0
Star
0
Code
Issues
2
Pull requests
0
Actions
Projects
0
Wiki
Security
Insights
Additional navigation options
Code
Issues
Pull requests
Actions
Projects
Wiki
Security
Insights
Files
ddc0d00
Documentation
arch
block
crypto
drivers
fs
include
acpi
asm-alpha
asm-arm
asm-avr32
asm-blackfin
asm-cris
asm-frv
asm-generic
asm-h8300
asm-ia64
asm-m32r
asm-m68k
asm-m68knommu
asm-mips
dec
emma2rh
fw
ip32
jmr3927
lasat
mach-atlas
mach-au1x00
mach-bcm47xx
mach-cobalt
mach-db1x00
mach-dec
mach-emma2rh
mach-excite
mach-generic
mach-ip22
mach-ip27
mach-ip28
mach-ip32
mach-jazz
mach-jmr3927
mach-lasat
mach-lemote
mach-mips
mach-mipssim
mach-pb1x00
mach-pnx8550
mach-rm
mach-sibyte
mach-tx49xx
mach-vr41xx
mach-wrppmc
mach-yosemite
mips-boards
pci
pmc-sierra
sgi
sibyte
sn
tx4927
tx4938
vr41xx
xtalk
Kbuild
a.out.h
abi.h
addrspace.h
asm.h
asmmacro-32.h
asmmacro-64.h
asmmacro.h
atomic.h
auxvec.h
barrier.h
bcache.h
bitops.h
bootinfo.h
branch.h
break.h
bug.h
bugs.h
byteorder.h
cache.h
cachectl.h
cacheflush.h
cacheops.h
checksum.h
cmp.h
cmpxchg.h
compat-signal.h
compat.h
compiler.h
cpu-features.h
cpu-info.h
cpu.h
cputime.h
current.h
debug.h
delay.h
device.h
div64.h
dma-mapping.h
dma.h
ds1286.h
ds1287.h
dsp.h
edac.h
elf.h
emergency-restart.h
errno.h
fb.h
fcntl.h
fixmap.h
floppy.h
fpregdef.h
fpu.h
fpu_emulator.h
futex.h
gcmpregs.h
gdb-stub.h
gic.h
gpio.h
gt64120.h
hardirq.h
hazards.h
highmem.h
hw_irq.h
i8253.h
i8259.h
ide.h
inst.h
inventory.h
io.h
ioctl.h
ioctls.h
ipcbuf.h
irq.h
irq_cpu.h
irq_gt641xx.h
irq_regs.h
irqflags.h
isadep.h
jazz.h
jazzdma.h
kdebug.h
kexec.h
kmap_types.h
kspd.h
kvm.h
linkage.h
local.h
m48t35.h
m48t37.h
mc146818-time.h
mc146818rtc.h
mips_mt.h
mipsmtregs.h
mipsprom.h
mipsregs.h
mman.h
mmu.h
mmu_context.h
mmzone.h
module.h
msc01_ic.h
msgbuf.h
mutex.h
namei.h
nile4.h
paccess.h
page.h
param.h
parport.h
pci.h
percpu.h
pgalloc.h
pgtable-32.h
pgtable-64.h
pgtable-bits.h
pgtable.h
pmon.h
poll.h
posix_types.h
prctl.h
prefetch.h
processor.h
ptrace.h
r4k-timer.h
r4kcache.h
reboot.h
reg.h
regdef.h
resource.h
rm9k-ocd.h
rtlx.h
scatterlist.h
seccomp.h
sections.h
segment.h
semaphore.h
sembuf.h
serial.h
setup.h
sgialib.h
sgiarcs.h
sgidefs.h
shmbuf.h
shmparam.h
sigcontext.h
siginfo.h
signal.h
sim.h
smp-ops.h
smp.h
smtc.h
smtc_ipi.h
smtc_proc.h
smvp.h
sni.h
socket.h
sockios.h
sparsemem.h
spinlock.h
spinlock_types.h
stackframe.h
stacktrace.h
stat.h
statfs.h
string.h
suspend.h
sysmips.h
system.h
termbits.h
termios.h
thread_info.h
time.h
timex.h
titan_dep.h
tlb.h
tlbdebug.h
tlbflush.h
topology.h
traps.h
txx9irq.h
txx9pio.h
txx9tmr.h
types.h
uaccess.h
ucontext.h
unaligned.h
unistd.h
user.h
vga.h
vpe.h
war.h
wbflush.h
xor.h
asm-mn10300
asm-parisc
asm-powerpc
asm-ppc
asm-s390
asm-sh
asm-sparc
asm-sparc64
asm-um
asm-v850
asm-x86
asm-xtensa
crypto
keys
linux
math-emu
media
mtd
net
pcmcia
rdma
rxrpc
scsi
sound
video
xen
Kbuild
init
ipc
kernel
lib
mm
net
samples
scripts
security
sound
usr
virt
.gitignore
.mailmap
COPYING
CREDITS
Kbuild
MAINTAINERS
Makefile
README
REPORTING-BUGS
Breadcrumbs
linux
/
include
/
asm-mips
/
bitops.h
Blame
Blame
Latest commit
History
History
672 lines (601 loc) · 16.1 KB
Breadcrumbs
linux
/
include
/
asm-mips
/
bitops.h
Top
File metadata and controls
Code
Blame
672 lines (601 loc) · 16.1 KB
Raw
/* * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * Copyright (c) 1994 - 1997, 99, 2000, 06, 07 Ralf Baechle (ralf@linux-mips.org) * Copyright (c) 1999, 2000 Silicon Graphics, Inc. */ #ifndef _ASM_BITOPS_H #define _ASM_BITOPS_H #ifndef _LINUX_BITOPS_H #error only <linux/bitops.h> can be included directly #endif #include <linux/compiler.h> #include <linux/irqflags.h> #include <linux/types.h> #include <asm/barrier.h> #include <asm/bug.h> #include <asm/byteorder.h> /* sigh ... */ #include <asm/cpu-features.h> #include <asm/sgidefs.h> #include <asm/war.h> #if _MIPS_SZLONG == 32 #define SZLONG_LOG 5 #define SZLONG_MASK 31UL #define __LL "ll " #define __SC "sc " #define __INS "ins " #define __EXT "ext " #elif _MIPS_SZLONG == 64 #define SZLONG_LOG 6 #define SZLONG_MASK 63UL #define __LL "lld " #define __SC "scd " #define __INS "dins " #define __EXT "dext " #endif /* * clear_bit() doesn't provide any barrier for the compiler. */ #define smp_mb__before_clear_bit() smp_llsc_mb() #define smp_mb__after_clear_bit() smp_llsc_mb() /* * set_bit - Atomically set a bit in memory * @nr: the bit to set * @addr: the address to start counting from * * This function is atomic and may not be reordered. See __set_bit() * if you do not require the atomic guarantees. * Note that @nr may be almost arbitrarily large; this function is not * restricted to acting on a single-word quantity. */ static inline void set_bit(unsigned long nr, volatile unsigned long *addr) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned short bit = nr & SZLONG_MASK; unsigned long temp; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set mips3 \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" " " __SC "%0, %1 \n" " beqzl %0, 1b \n" " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << bit), "m" (*m)); #ifdef CONFIG_CPU_MIPSR2 } else if (__builtin_constant_p(bit)) { __asm__ __volatile__( "1: " __LL "%0, %1 # set_bit \n" " " __INS "%0, %4, %2, 1 \n" " " __SC "%0, %1 \n" " beqz %0, 2f \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m) : "ir" (bit), "m" (*m), "r" (~0)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (cpu_has_llsc) { __asm__ __volatile__( " .set mips3 \n" "1: " __LL "%0, %1 # set_bit \n" " or %0, %2 \n" " " __SC "%0, %1 \n" " beqz %0, 2f \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << bit), "m" (*m)); } else { volatile unsigned long *a = addr; unsigned long mask; unsigned long flags; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); *a |= mask; raw_local_irq_restore(flags); } } /* * clear_bit - Clears a bit in memory * @nr: Bit to clear * @addr: Address to start counting from * * clear_bit() is atomic and may not be reordered. However, it does * not contain a memory barrier, so if it is used for locking purposes, * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit() * in order to ensure changes are visible on other processors. */ static inline void clear_bit(unsigned long nr, volatile unsigned long *addr) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned short bit = nr & SZLONG_MASK; unsigned long temp; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set mips3 \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" " beqzl %0, 1b \n" " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (~(1UL << bit)), "m" (*m)); #ifdef CONFIG_CPU_MIPSR2 } else if (__builtin_constant_p(bit)) { __asm__ __volatile__( "1: " __LL "%0, %1 # clear_bit \n" " " __INS "%0, $0, %2, 1 \n" " " __SC "%0, %1 \n" " beqz %0, 2f \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m) : "ir" (bit), "m" (*m)); #endif /* CONFIG_CPU_MIPSR2 */ } else if (cpu_has_llsc) { __asm__ __volatile__( " .set mips3 \n" "1: " __LL "%0, %1 # clear_bit \n" " and %0, %2 \n" " " __SC "%0, %1 \n" " beqz %0, 2f \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (~(1UL << bit)), "m" (*m)); } else { volatile unsigned long *a = addr; unsigned long mask; unsigned long flags; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); *a &= ~mask; raw_local_irq_restore(flags); } } /* * clear_bit_unlock - Clears a bit in memory * @nr: Bit to clear * @addr: Address to start counting from * * clear_bit() is atomic and implies release semantics before the memory * operation. It can be used for an unlock. */ static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr) { smp_mb__before_clear_bit(); clear_bit(nr, addr); } /* * change_bit - Toggle a bit in memory * @nr: Bit to change * @addr: Address to start counting from * * change_bit() is atomic and may not be reordered. * Note that @nr may be almost arbitrarily large; this function is not * restricted to acting on a single-word quantity. */ static inline void change_bit(unsigned long nr, volatile unsigned long *addr) { unsigned short bit = nr & SZLONG_MASK; if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( " .set mips3 \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" " " __SC "%0, %1 \n" " beqzl %0, 1b \n" " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << bit), "m" (*m)); } else if (cpu_has_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( " .set mips3 \n" "1: " __LL "%0, %1 # change_bit \n" " xor %0, %2 \n" " " __SC "%0, %1 \n" " beqz %0, 2f \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" " .set mips0 \n" : "=&r" (temp), "=m" (*m) : "ir" (1UL << bit), "m" (*m)); } else { volatile unsigned long *a = addr; unsigned long mask; unsigned long flags; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); *a ^= mask; raw_local_irq_restore(flags); } } /* * test_and_set_bit - Set a bit and return its old value * @nr: Bit to set * @addr: Address to count from * * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ static inline int test_and_set_bit(unsigned long nr, volatile unsigned long *addr) { unsigned short bit = nr & SZLONG_MASK; unsigned long res; smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( " .set mips3 \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); } else if (cpu_has_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( " .set push \n" " .set noreorder \n" " .set mips3 \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqz %2, 2f \n" " and %2, %0, %3 \n" " .subsection 2 \n" "2: b 1b \n" " nop \n" " .previous \n" " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); } else { volatile unsigned long *a = addr; unsigned long mask; unsigned long flags; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); res = (mask & *a); *a |= mask; raw_local_irq_restore(flags); } smp_llsc_mb(); return res != 0; } /* * test_and_set_bit_lock - Set a bit and return its old value * @nr: Bit to set * @addr: Address to count from * * This operation is atomic and implies acquire ordering semantics * after the memory operation. */ static inline int test_and_set_bit_lock(unsigned long nr, volatile unsigned long *addr) { unsigned short bit = nr & SZLONG_MASK; unsigned long res; if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( " .set mips3 \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); } else if (cpu_has_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( " .set push \n" " .set noreorder \n" " .set mips3 \n" "1: " __LL "%0, %1 # test_and_set_bit \n" " or %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqz %2, 2f \n" " and %2, %0, %3 \n" " .subsection 2 \n" "2: b 1b \n" " nop \n" " .previous \n" " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); } else { volatile unsigned long *a = addr; unsigned long mask; unsigned long flags; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); res = (mask & *a); *a |= mask; raw_local_irq_restore(flags); } smp_llsc_mb(); return res != 0; } /* * test_and_clear_bit - Clear a bit and return its old value * @nr: Bit to clear * @addr: Address to count from * * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ static inline int test_and_clear_bit(unsigned long nr, volatile unsigned long *addr) { unsigned short bit = nr & SZLONG_MASK; unsigned long res; smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( " .set mips3 \n" "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); #ifdef CONFIG_CPU_MIPSR2 } else if (__builtin_constant_p(nr)) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( "1: " __LL "%0, %1 # test_and_clear_bit \n" " " __EXT "%2, %0, %3, 1 \n" " " __INS "%0, $0, %3, 1 \n" " " __SC "%0, %1 \n" " beqz %0, 2f \n" " .subsection 2 \n" "2: b 1b \n" " .previous \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "ri" (bit), "m" (*m) : "memory"); #endif } else if (cpu_has_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( " .set push \n" " .set noreorder \n" " .set mips3 \n" "1: " __LL "%0, %1 # test_and_clear_bit \n" " or %2, %0, %3 \n" " xor %2, %3 \n" " " __SC "%2, %1 \n" " beqz %2, 2f \n" " and %2, %0, %3 \n" " .subsection 2 \n" "2: b 1b \n" " nop \n" " .previous \n" " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); } else { volatile unsigned long *a = addr; unsigned long mask; unsigned long flags; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); res = (mask & *a); *a &= ~mask; raw_local_irq_restore(flags); } smp_llsc_mb(); return res != 0; } /* * test_and_change_bit - Change a bit and return its old value * @nr: Bit to change * @addr: Address to count from * * This operation is atomic and cannot be reordered. * It also implies a memory barrier. */ static inline int test_and_change_bit(unsigned long nr, volatile unsigned long *addr) { unsigned short bit = nr & SZLONG_MASK; unsigned long res; smp_llsc_mb(); if (cpu_has_llsc && R10000_LLSC_WAR) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( " .set mips3 \n" "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" " " __SC "%2, %1 \n" " beqzl %2, 1b \n" " and %2, %0, %3 \n" " .set mips0 \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); } else if (cpu_has_llsc) { unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG); unsigned long temp; __asm__ __volatile__( " .set push \n" " .set noreorder \n" " .set mips3 \n" "1: " __LL "%0, %1 # test_and_change_bit \n" " xor %2, %0, %3 \n" " " __SC "\t%2, %1 \n" " beqz %2, 2f \n" " and %2, %0, %3 \n" " .subsection 2 \n" "2: b 1b \n" " nop \n" " .previous \n" " .set pop \n" : "=&r" (temp), "=m" (*m), "=&r" (res) : "r" (1UL << bit), "m" (*m) : "memory"); } else { volatile unsigned long *a = addr; unsigned long mask; unsigned long flags; a += nr >> SZLONG_LOG; mask = 1UL << bit; raw_local_irq_save(flags); res = (mask & *a); *a ^= mask; raw_local_irq_restore(flags); } smp_llsc_mb(); return res != 0; } #include <asm-generic/bitops/non-atomic.h> /* * __clear_bit_unlock - Clears a bit in memory * @nr: Bit to clear * @addr: Address to start counting from * * __clear_bit() is non-atomic and implies release semantics before the memory * operation. It can be used for an unlock if no other CPUs can concurrently * modify other bits in the word. */ static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr) { smp_mb(); __clear_bit(nr, addr); } #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) /* * Return the bit position (0..63) of the most significant 1 bit in a word * Returns -1 if no 1 bit exists */ static inline unsigned long __fls(unsigned long x) { int lz; if (sizeof(x) == 4) { __asm__( " .set push \n" " .set mips32 \n" " clz %0, %1 \n" " .set pop \n" : "=r" (lz) : "r" (x)); return 31 - lz; } BUG_ON(sizeof(x) != 8); __asm__( " .set push \n" " .set mips64 \n" " dclz %0, %1 \n" " .set pop \n" : "=r" (lz) : "r" (x)); return 63 - lz; } /* * __ffs - find first bit in word. * @word: The word to search * * Returns 0..SZLONG-1 * Undefined if no bit exists, so code should check against 0 first. */ static inline unsigned long __ffs(unsigned long word) { return __fls(word & -word); } /* * fls - find last bit set. * @word: The word to search * * This is defined the same way as ffs. * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32. */ static inline int fls(int word) { __asm__("clz %0, %1" : "=r" (word) : "r" (word)); return 32 - word; } #if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64) static inline int fls64(__u64 word) { __asm__("dclz %0, %1" : "=r" (word) : "r" (word)); return 64 - word; } #else #include <asm-generic/bitops/fls64.h> #endif /* * ffs - find first bit set. * @word: The word to search * * This is defined the same way as * the libc and compiler builtin ffs routines, therefore * differs in spirit from the above ffz (man ffs). */ static inline int ffs(int word) { if (!word) return 0; return fls(word & -word); } #else #include <asm-generic/bitops/__ffs.h> #include <asm-generic/bitops/__fls.h> #include <asm-generic/bitops/ffs.h> #include <asm-generic/bitops/fls.h> #include <asm-generic/bitops/fls64.h> #endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */ #include <asm-generic/bitops/ffz.h> #include <asm-generic/bitops/find.h> #ifdef __KERNEL__ #include <asm-generic/bitops/sched.h> #include <asm-generic/bitops/hweight.h> #include <asm-generic/bitops/ext2-non-atomic.h> #include <asm-generic/bitops/ext2-atomic.h> #include <asm-generic/bitops/minix.h> #endif /* __KERNEL__ */ #endif /* _ASM_BITOPS_H */
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
You can’t perform that action at this time.