Skip to content
Navigation Menu
Toggle navigation
Sign in
In this repository
All GitHub Enterprise
↵
Jump to
↵
No suggested jump to results
In this repository
All GitHub Enterprise
↵
Jump to
↵
In this organization
All GitHub Enterprise
↵
Jump to
↵
In this repository
All GitHub Enterprise
↵
Jump to
↵
Sign in
Reseting focus
You signed in with another tab or window.
Reload
to refresh your session.
You signed out in another tab or window.
Reload
to refresh your session.
You switched accounts on another tab or window.
Reload
to refresh your session.
Dismiss alert
{{ message }}
mariux64
/
linux
Public
Notifications
You must be signed in to change notification settings
Fork
0
Star
0
Code
Issues
2
Pull requests
0
Actions
Projects
0
Wiki
Security
Insights
Additional navigation options
Code
Issues
Pull requests
Actions
Projects
Wiki
Security
Insights
Files
e515b47
Documentation
arch
alpha
arc
arm
arm64
avr32
blackfin
c6x
cris
frv
hexagon
ia64
m32r
m68k
metag
microblaze
mips
alchemy
ar7
ath79
bcm47xx
bcm63xx
boot
cavium-octeon
cobalt
configs
dec
emma
fw
include
asm
dec
emma
fw
ip32
lasat
mach-ar7
mach-ath79
mach-au1x00
mach-bcm47xx
mach-bcm63xx
mach-cavium-octeon
mach-cobalt
mach-db1x00
mach-dec
mach-emma2rh
mach-generic
mach-ip22
mach-ip27
mach-ip28
mach-ip32
mach-jazz
mach-jz4740
mach-lantiq
mach-lasat
mach-loongson
mach-loongson1
mach-malta
mach-netlogic
mach-pmcs-msp71xx
mach-pnx833x
mach-ralink
mach-rc32434
mach-rm
mach-sead3
mach-sibyte
mach-tx39xx
mach-tx49xx
mach-vr41xx
mips-boards
netlogic
octeon
pci
sgi
sibyte
sn
txx9
vr41xx
xtalk
Kbuild
abi.h
addrspace.h
amon.h
arch_hweight.h
asm-offsets.h
asm.h
asmmacro-32.h
asmmacro-64.h
asmmacro.h
atomic.h
barrier.h
bcache.h
bitops.h
bmips.h
bootinfo.h
branch.h
break.h
bug.h
bugs.h
cache.h
cacheflush.h
cacheops.h
cevt-r4k.h
checksum.h
clkdev.h
clock.h
cmp.h
cmpxchg.h
compat-signal.h
compat.h
compiler.h
cop2.h
cpu-features.h
cpu-info.h
cpu-type.h
cpu.h
debug.h
delay.h
device.h
div64.h
dma-coherence.h
dma-mapping.h
dma.h
ds1287.h
dsp.h
edac.h
elf.h
errno.h
exec.h
fb.h
fixmap.h
floppy.h
fpregdef.h
fpu.h
fpu_emulator.h
ftrace.h
futex.h
gcmpregs.h
gic.h
gio_device.h
gpio.h
gt64120.h
hardirq.h
hazards.h
highmem.h
hugetlb.h
hw_irq.h
i8259.h
ide.h
idle.h
inst.h
io.h
irq.h
irq_cpu.h
irq_gt641xx.h
irq_regs.h
irqflags.h
isadep.h
jazz.h
jazzdma.h
jump_label.h
kdebug.h
kexec.h
kgdb.h
kmap_types.h
kprobes.h
kvm_host.h
linkage.h
local.h
m48t37.h
mc146818-time.h
mc146818rtc.h
mips_machine.h
mips_mt.h
mipsmtregs.h
mipsprom.h
mipsregs.h
mmu.h
mmu_context.h
mmzone.h
module.h
msc01_ic.h
nile4.h
paccess.h
page.h
pci.h
perf_event.h
pgalloc.h
pgtable-32.h
pgtable-64.h
pgtable-bits.h
pgtable.h
pmon.h
prefetch.h
processor.h
prom.h
ptrace.h
r4k-timer.h
r4kcache.h
reboot.h
reg.h
regdef.h
rm9k-ocd.h
rtlx.h
seccomp.h
setup.h
sgialib.h
sgiarcs.h
shmparam.h
sigcontext.h
siginfo.h
signal.h
sim.h
smp-ops.h
smp.h
smtc.h
smtc_ipi.h
smtc_proc.h
sni.h
socket.h
sparsemem.h
spinlock.h
spinlock_types.h
spram.h
stackframe.h
stackprotector.h
stacktrace.h
string.h
suspend.h
switch_to.h
syscall.h
termios.h
thread_info.h
time.h
timex.h
tlb.h
tlbdebug.h
tlbflush.h
tlbmisc.h
topology.h
traps.h
txx9irq.h
txx9pio.h
txx9tmr.h
types.h
uaccess.h
uasm.h
unaligned.h
unistd.h
user.h
vdso.h
vga.h
vpe.h
war.h
watch.h
wbflush.h
uapi
jazz
jz4740
kernel
kvm
lantiq
lasat
lib
loongson
loongson1
math-emu
mm
mti-malta
mti-sead3
netlogic
oprofile
pci
pmcs-msp71xx
pnx833x
power
ralink
rb532
sgi-ip22
sgi-ip27
sgi-ip32
sibyte
sni
txx9
vr41xx
Kbuild
Kbuild.platforms
Kconfig
Kconfig.debug
Makefile
mn10300
openrisc
parisc
powerpc
s390
score
sh
sparc
tile
um
unicore32
x86
xtensa
.gitignore
Kconfig
block
crypto
drivers
firmware
fs
include
init
ipc
kernel
lib
mm
net
samples
scripts
security
sound
tools
usr
virt
.gitignore
.mailmap
COPYING
CREDITS
Kbuild
Kconfig
MAINTAINERS
Makefile
README
REPORTING-BUGS
Breadcrumbs
linux
/
arch
/
mips
/
include
/
asm
/
cacheops.h
Blame
Blame
Latest commit
History
History
88 lines (80 loc) · 2.22 KB
Breadcrumbs
linux
/
arch
/
mips
/
include
/
asm
/
cacheops.h
Top
File metadata and controls
Code
Blame
88 lines (80 loc) · 2.22 KB
Raw
/* * Cache operations for the cache instruction. * * This file is subject to the terms and conditions of the GNU General Public * License. See the file "COPYING" in the main directory of this archive * for more details. * * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle * (C) Copyright 1999 Silicon Graphics, Inc. */ #ifndef __ASM_CACHEOPS_H #define __ASM_CACHEOPS_H /* * Cache Operations available on all MIPS processors with R4000-style caches */ #define Index_Invalidate_I 0x00 #define Index_Writeback_Inv_D 0x01 #define Index_Load_Tag_I 0x04 #define Index_Load_Tag_D 0x05 #define Index_Store_Tag_I 0x08 #define Index_Store_Tag_D 0x09 #define Hit_Invalidate_I 0x10 #define Hit_Invalidate_D 0x11 #define Hit_Writeback_Inv_D 0x15 /* * R4000-specific cacheops */ #define Create_Dirty_Excl_D 0x0d #define Fill 0x14 #define Hit_Writeback_I 0x18 #define Hit_Writeback_D 0x19 /* * R4000SC and R4400SC-specific cacheops */ #define Index_Invalidate_SI 0x02 #define Index_Writeback_Inv_SD 0x03 #define Index_Load_Tag_SI 0x06 #define Index_Load_Tag_SD 0x07 #define Index_Store_Tag_SI 0x0A #define Index_Store_Tag_SD 0x0B #define Create_Dirty_Excl_SD 0x0f #define Hit_Invalidate_SI 0x12 #define Hit_Invalidate_SD 0x13 #define Hit_Writeback_Inv_SD 0x17 #define Hit_Writeback_SD 0x1b #define Hit_Set_Virtual_SI 0x1e #define Hit_Set_Virtual_SD 0x1f /* * R5000-specific cacheops */ #define R5K_Page_Invalidate_S 0x17 /* * RM7000-specific cacheops */ #define Page_Invalidate_T 0x16 #define Index_Store_Tag_T 0x0a #define Index_Load_Tag_T 0x06 /* * R10000-specific cacheops * * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused. * Most of the _S cacheops are identical to the R4000SC _SD cacheops. */ #define Index_Writeback_Inv_S 0x03 #define Index_Load_Tag_S 0x07 #define Index_Store_Tag_S 0x0B #define Hit_Invalidate_S 0x13 #define Cache_Barrier 0x14 #define Hit_Writeback_Inv_S 0x17 #define Index_Load_Data_I 0x18 #define Index_Load_Data_D 0x19 #define Index_Load_Data_S 0x1b #define Index_Store_Data_I 0x1c #define Index_Store_Data_D 0x1d #define Index_Store_Data_S 0x1f /* * Loongson2-specific cacheops */ #define Hit_Invalidate_I_Loongson2 0x00 #endif /* __ASM_CACHEOPS_H */
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
You can’t perform that action at this time.