From 070e246217230cce21b8dddad38bd59428494c48 Mon Sep 17 00:00:00 2001 From: Phil Edworthy Date: Fri, 22 Apr 2022 20:06:15 +0200 Subject: [PATCH] serial: 8250: dw: Improve RZN1 support Renesas RZ/N1 SoC features a slightly modified DW UART. On this SoC, the CPR register value is known but not synthetized in hardware. We hence need to provide a CPR value in the platform data. This version of the controller also relies on acting as flow controller when using DMA, so we need to provide the "is dma flow controller" quirk. Co-developed-by: Miquel Raynal Reviewed-by: Andy Shevchenko Signed-off-by: Phil Edworthy Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/r/20220422180615.9098-10-miquel.raynal@bootlin.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/8250/8250_dw.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/tty/serial/8250/8250_dw.c b/drivers/tty/serial/8250/8250_dw.c index 90e64c8bd4bf0..0cf1a99dc1244 100644 --- a/drivers/tty/serial/8250/8250_dw.c +++ b/drivers/tty/serial/8250/8250_dw.c @@ -761,6 +761,8 @@ static const struct dw8250_platform_data dw8250_armada_38x_data = { static const struct dw8250_platform_data dw8250_renesas_rzn1_data = { .usr_reg = DW_UART_USR, + .cpr_val = 0x00012f32, + .quirks = DW_UART_QUIRK_IS_DMA_FC, }; static const struct dw8250_platform_data dw8250_starfive_jh7100_data = {