From 0a0c5d13617fb52a66c4980f40faa42a1007d3b4 Mon Sep 17 00:00:00 2001
From: Yuantian Tang <andy.tang@nxp.com>
Date: Wed, 15 Jul 2020 14:49:09 +0800
Subject: [PATCH] arm64: dts: ls208xa: add more thermal zone support
There are 7 thermal zones in ls208xa soc. Add the other thermal zone
nodes to enable them.
Signed-off-by: Yuantian Tang <andy.tang@nxp.com>
Reviewed-by: Amit Kucheria <amitk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
---
.../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 141 ++++++++++++++++--
1 file changed, 132 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 41102dacc2e10..cc36c969dd9dd 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -79,20 +79,62 @@
};
thermal-zones {
- cpu_thermal: cpu-thermal {
+ ddr-controller1 {
polling-delay-passive = <1000>;
polling-delay = <5000>;
+ thermal-sensors = <&tmu 1>;
+ trips {
+ ddr-ctrler1-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-controller2 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 2>;
+
+ trips {
+ ddr-ctrler2-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ ddr-controller3 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 3>;
+
+ trips {
+ ddr-ctrler3-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+ };
+
+ core-cluster1 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
thermal-sensors = <&tmu 4>;
trips {
- cpu_alert: cpu-alert {
- temperature = <75000>;
+ core_cluster1_alert: core-cluster1-alert {
+ temperature = <85000>;
hysteresis = <2000>;
type = "passive";
};
- cpu_crit: cpu-crit {
- temperature = <85000>;
+
+ core-cluster1-crit {
+ temperature = <95000>;
hysteresis = <2000>;
type = "critical";
};
@@ -100,14 +142,95 @@
cooling-maps {
map0 {
- trip = <&cpu_alert>;
+ trip = <&core_cluster1_alert>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ core-cluster2 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 5>;
+
+ trips {
+ core_cluster2_alert: core-cluster2-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ core-cluster2-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&core_cluster2_alert>;
+ cooling-device =
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ core-cluster3 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 6>;
+
+ trips {
+ core_cluster3_alert: core-cluster3-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ core-cluster3-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&core_cluster3_alert>;
+ cooling-device =
<&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
- <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+
+ core-cluster4 {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+ thermal-sensors = <&tmu 7>;
+
+ trips {
+ core_cluster4_alert: core-cluster4-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ core-cluster4-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&core_cluster4_alert>;
+ cooling-device =
<&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};