diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_debug.c index 2f9c943f12d56..5e35033ba3e43 100644 --- a/drivers/gpu/drm/msm/dp/dp_debug.c +++ b/drivers/gpu/drm/msm/dp/dp_debug.c @@ -44,8 +44,6 @@ static int dp_debug_show(struct seq_file *seq, void *p) drm_mode = &debug->panel->dp_mode.drm_mode; seq_printf(seq, "\tname = %s\n", DEBUG_NAME); - seq_printf(seq, "\tdp_panel\n\t\tmax_pclk_khz = %d\n", - debug->panel->max_pclk_khz); seq_printf(seq, "\tdrm_dp_link\n\t\trate = %u\n", debug->panel->link_info.rate); seq_printf(seq, "\t\tnum_lanes = %u\n", diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index a3ed0295afce6..0b1d62a033dc9 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -377,7 +377,6 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) dp->audio_supported = drm_detect_monitor_audio(edid); dp_panel_handle_sink_request(dp->panel); - dp->dp_display.max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ; dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes; /* @@ -1006,9 +1005,7 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, return -EINVAL; } - if ((dp->max_pclk_khz <= 0) || - (dp->max_pclk_khz > DP_MAX_PIXEL_CLK_KHZ) || - (mode->clock > dp->max_pclk_khz)) + if (mode->clock > DP_MAX_PIXEL_CLK_KHZ) return MODE_BAD; dp_display = container_of(dp, struct dp_display_private, dp_display); diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 03c85779de4b2..f1adf2b84975a 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -26,8 +26,6 @@ struct msm_dp { bool wide_bus_en; - u32 max_pclk_khz; - u32 max_dp_lanes; struct dp_audio *dp_audio; }; diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index 9fa6e524832c9..d861197ac1c8f 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -49,7 +49,6 @@ struct dp_panel { bool video_test; u32 vic; - u32 max_pclk_khz; u32 max_dp_lanes; u32 max_bw_code;