From 21ebe64a2450fa1875e3c24fe137b598e96b81e3 Mon Sep 17 00:00:00 2001 From: Gregory CLEMENT Date: Thu, 23 Jan 2025 12:01:54 +0100 Subject: [PATCH] dt-bindings: mips: Document mti,mips-cm Add device tree binding documentation for MIPS Coherence Manager. This component enables support for SMP by providing each processor in the system with a uniform view of memory. The Coherence Manager is responsible for establishing the global ordering of requests from all elements of the system and sending the correct data back to the requester. Based on the work of Jiaxun Yang Signed-off-by: Gregory CLEMENT Reviewed-by: Rob Herring (Arm) Signed-off-by: Thomas Bogendoerfer --- .../devicetree/bindings/mips/mti,mips-cm.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mti,mips-cm.yaml diff --git a/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml new file mode 100644 index 0000000000000..4324b2306535f --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mti,mips-cm.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mti,mips-cm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MIPS Coherence Manager + +description: + The Coherence Manager (CM) is responsible for establishing the + global ordering of requests from all elements of the system and + sending the correct data back to the requester. It supports Cache + to Cache transfers. + https://training.mips.com/cps_mips/PDF/CPS_Introduction.pdf + https://training.mips.com/cps_mips/PDF/Coherency_Manager.pdf + +maintainers: + - Jiaxun Yang + +properties: + compatible: + const: mti,mips-cm + + reg: + description: + Base address and size of the Global Configuration Registers + referred to as CMGCR.They are the system programmer's interface + to the Coherency Manager. Their location in the memory map is + determined at core build time. In a functional system, the base + address is provided by the Coprocessor 0, but some + System-on-Chip (SoC) designs may not provide an accurate address + that needs to be described statically. + + maxItems: 1 + +required: + - compatible + +additionalProperties: false + +examples: + - | + coherency-manager@1fbf8000 { + compatible = "mti,mips-cm"; + reg = <0x1bde8000 0x8000>; + }; +...